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AR# 18349

11.1 EDK - "ERROR:MDT - ...\system.mhs line xx Invalid Signal name sig_name[0] -- PlatGen doesn't support vector slicing"

Description

When I try to connect a signal using the following syntax in my MHS file:

PORT B = mysig[0]

I receive the following error message:

"ERROR:MDT - ...\system.mhs line xx Invalid Signal name sig_name[0] -- PlatGen doesn't support vector slicing."

Solution

It is not valid to splice a signal into smaller signals using [ ] notation. Use signal concatenation (&) operator or util_bus_split IP instead.

util_bus_split IP can be found in the following location:

C:\<EDK_Installation_Directory>\hw\XilinxProcessorIPLib\pcores\util_bus_split_v1_00_a

This core splits a bus into individual signals.

Incorrect:

---------------

PORT A = mysig # a 2-bit signal

PORT B = mysig[0] # invalid syntax []

PORT C = mysig[1]

Correct:

------------

PORT A = mysig_0 & mysig_1

PORT B = mysig_0

PORT C = mysig_1

mysig_0 and mysig_1 are the outputs from an instance of util_bus_split core.

Refer to (Xilinx Answer 19133) for additional information.

AR# 18349
Date Created 09/03/2007
Last Updated 12/15/2012
Status Active
Type General Article