.v line xx Too many parameter assignments in instance 'A' of module 'C'"">
When compiling a Verilog design in XST, the following error might occur:
"ERROR:HDLCompilers:90 - <file>.v line xx Too many parameter assignments in instance 'A' of module 'C'"
Parameter overrides can be used with instantiations to override a parameter value assigned in the instantiated submodule. You can do this by using the # sign, as shown below:
lower #(8) u1 (.i(data), .o(value));
or the defparam statement:
lower u1 (.i(data), .o(value));
defparam u1.myparam = 8;
If the first method is used and the submodule does not have any or enough parameters, the error listed above occurs. This is most commonly seen with instantiations of RAM or LUT components from the Xilinx library, but can easily exist with user-defined submodules as well.
To avoid the problem, ensure that the submodule has the correct number of parameters declared. Note that XST (as of 6.1i) does not yet have parameters in the "unisim_comp.v" library. To assign INIT values to RAM or LUT components, the standard XST attribute syntax should be employed as described in (Xilinx Answer 11069).