We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 18403

6.1i Floorplanner - After PAR Floorplanner shows the logic, it does not display the I/O pins to which it connects


Keywords: Floorplanner, I/O, pin, connect, missing, listed, PAR, IBM FPGA

Urgency: Standard

General Description:
I can run my design through the implementation tools with no problems. However, after PAR, I open FloorPlanner to see the logic and I/Os, and I can see only where the logic is placed and not where it is connected. Floorplanner does not show which I/O pins it connects to. The "Design Hierarchy" window on the left side of Floorplanner does list the IOBs.


This issue is fixed in a Service Pack for the 6.1i tools. The service pack containing the fix is SP3 (6.1.03i).

This problem has been fixed in the latest 6.1i Service Pack available at:
The first service pack containing the fix is 6.1i Service Pack 3.
AR# 18403
Date Created 11/12/2003
Last Updated 02/21/2007
Status Archive
Type General Article