UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 18423

LogiCORE Asynchronous FIFO v5.1 - Why are the Verilog simulation model almost empty and almost full flags not synchronous to RD_CLK?

Description

Why are the Verilog simulation model almost empty and almost full flags not synchronous to RD_CLK?

Solution

The EMPTY and ALMOST_EMPTY flags are supposed to be synchronous to RD_CLK, and the FULL and ALMOST_FULL flags are supposed to be synchronous to the WR_CLK. However, these flags all trigger on: 

@(posedge wr_pulse or posedge rd_pulse or posedge AINIT) 

 

As a result, these flags are switching on both RD_CLK and WR_CLK. For example, the EMPTY flag is asserted on the RD_CLK, and deasserted on the WR_CLK.

AR# 18423
Date Created 09/03/2007
Last Updated 05/16/2014
Status Archive
Type General Article