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AR# 18444

6.1i UniSim - Lock pin of DLL does not go High during behavioral simulation


Keywords: UniSim, DLL, lock, high, Verilog

Urgency: Standard

General Description:
During a Verilog behavioral simulation of a DLL, the lock pin does not go High; however, the CLK0 output seems to be correct. This happens if the duty-cycle of the input clock is 1/5.


This was seen to be a problem in the simulation libraries, and it has been fixed in the 6.2i release.
AR# 18444
Date Created 09/03/2007
Last Updated 11/18/2008
Status Archive
Type General Article