We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 18452

7.1i XST - "WARNING:Xst:1960 - file.vhd line xx: Potential simulation mismatch, variable yy declared in block blck1 is assigned in block blck2"


Keywords: VHDL, global, variable, shared, sharing, multiple procedures

Urgency: Standard

General Description:
XST currently does not produce a netlist that agrees with simulation when a variable is declared in a function and then the variable is used in multiple procedures that are created inside of the same function:

Function global (.....)
variable glob_var : ....

procedure sub1 (...)
glob_var := glob_var + 1;
end procedure;

procedure sub2 (...)
glob_var := glob_var + 2;
end procedure;

sub1 (...);
sub2 (...)
if (glob_var == 1) then .....
end function


To work around this issue, avoid sharing the variable with multiple procedures inside a function. That is, pass the value of the variable that is declared in the function to a variable that is declared locally within the procedure.
AR# 18452
Date Created 09/03/2007
Last Updated 01/07/2009
Status Archive
Type General Article