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AR# 18517

XST - How can I reduce the resource use when using a synchronous and an asynchronous reset?

Description

Combining synchronous and asynchronous reset uses a lot of resources. How can I minimize the resource usage?

Solution

Verilog

module new_async_soft_reset(a_in,b_out,async_reset,soft_reset,clock);

input a_in;

input async_reset;

input soft_reset;

input clock;

output b_out;

reg b_out;

reg soft_reset_reg ;

wire reset_all ;

assign reset_all = soft_reset_reg | async_reset ;

always @(posedge clock or posedge async_reset)

begin

if (async_reset)

soft_reset_reg <= 1'b0;

else

soft_reset_reg <= soft_reset;

end

always @(posedge clock or negedge reset_all)

begin

if (~reset_all)

b_out <= 1'b0;

else

b_out <= a_in;

end

endmodule

VHDL

library ieee;

use ieee.std_logic_1164.all;

entity new_async_soft_reset is

port (a_in, async_reset, soft_reset, clock : in std_logic;

b_out : out std_logic);

end entity;

architecture new_async_soft_reset_arch of new_async_soft_reset is

signal soft_reset_reg, reset_all : std_logic;

begin

reset_all <= soft_reset_reg OR async_reset;

process (clock, async_reset) is

begin

if async_reset = '1' then

soft_reset_reg <= '0';

elsif clock'event and clock = '1' then

soft_reset_reg <= soft_reset;

end if;

end process;

process (clock, reset_all) is

begin

if reset_all = '0' then

b_out <= '0';

elsif clock'event and clock = '1' then

b_out <= a_in;

end if;

end process;

end architecture;

AR# 18517
Date Created 09/03/2007
Last Updated 12/15/2012
Status Active
Type General Article