We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 18519

6.1is2 Timing/PAR - PAR failed with a "WARNING:Timing:2666 - Constraint ignored..."


General Description:

When I was implementing my design, in the timing state of PAR, I received the following messages:

"WARNING:Timing:2666 - Constraint ignored: PATH "FROM clk_36_buf TO clk_144_buf" TIG ;

ERROR: PAR failed

Process "Place & Route" did not complete."

When will this be fixed?


This problem has been fixed in the latest 6.1i Service Pack available at:

The first service pack containing the fix is 6.1i Service Pack 3.

AR# 18519
Date Created 09/03/2007
Last Updated 01/18/2010
Status Archive
Type General Article