When I was implementing my design, in the timing state of PAR, I received the following messages:
"WARNING:Timing:2666 - Constraint ignored: PATH "FROM clk_36_buf TO clk_144_buf" TIG ;
ERROR: PAR failed
Process "Place & Route" did not complete."
When will this be fixed?
This problem has been fixed in the latest 6.1i Service Pack available at:
The first service pack containing the fix is 6.1i Service Pack 3.