We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 18530

LogiCORE PCI Express - Simulation with the non-fast_train simulation model does not work; the core does not train


When simulating the PCI Express Corel, it does not seem to train.


During training there are multiple millisecond timeouts in the LTSSM. For more information on this, review section 4.2.6 of the PCI Base Specification v1.0a. For example, in some states polling takes up to 24 ms to complete. If the timeouts from each state are added, the training time is extremely long for simulation. You can bypass the timeout counters by setting the "Fast Train Simulation" input to the core to "1". By setting the input to "1", the simulation can complete training and you can concentrate on data transfers. Once your design is placed on the board, the input should be set back to "0" so that the training can occur as normal. You cannot use the fast train simulation mode in hardware.

For the cores delivered through CORE Generator, pci_exp_8_lane_64b_ep, pci_exp_4_lane_32b_ep, and pci_exp_1_lane_32b_ep, there is an input to the core called fast_train_simulation_only. This input should be set to "1" for simulation and to "0" for synthesis.

For the cores delivered through the Web site, pci_exp_4_lane_64b_ep and pci_exp_1_lane_64b_ep, configuration vector bit 507 should be set to "1" for simulation and to "0" for synthesis.

AR# 18530
Date Created 09/03/2007
Last Updated 12/15/2012
Status Active
Type General Article