We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 18554

v1.3 Aurora 804 Reference Design - Link resets without any errors occurring


Urgency: Hot  


General Description: 

If the sequence 0x4A is sent at the beginning of a packet following an idle period, or 0x4A is sent at the end of a packet that is then followed by an idle period, the Aurora Core can reset.


This problem is due to a bug in the Aurora 804 Core. A patch can be obtained at: 


The Aurora 804 Core is being replaced by the COREGen Aurora Generator, so the patch will not be released into the 804 code.

AR# 18554
Date Created 09/03/2007
Last Updated 05/16/2014
Status Archive
Type General Article