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AR# 18559

6.1 EDK - Top-level ports can be reordered in 6.1 EDK designs migrated from version 3.2


Keywords: MHS, PlatGen, VHDL, EDK, reorder

Urgency: Hot

General Description:
In 3.2 EDK, PlatGen modifies the "endianess/notation" of the MHS top-level to match the MPD. This changed in 6.1 EDK so that PlatGen no longer makes this assumption.


In 3.2 EDK, PlatGen modifies the "endianess/notation" of the MHS top-level port assignment to match that of the MPD.

Given a top-level port of [0:3]:

PORT phy_txd = phy_txd, DIR = IN, VEC = [0:3]

PlatGen 3.2 would write out the top-level HDL port at the entity as:

phy_txd : in std_logic_vector(3 downto 0)

in order to match the MPD port VEC definition. However, this changes your top-level port interface.

This changed in 6.1 EDK, as PlatGen no longer makes this assumption. If your design relied on this in version 3.2, it will break in version 6.1.

To find out if your design is potentially affected, compare the MHS VEC notation of the global bus ports with their VEC notation in the MPD file. Be sure that the VEC notations match.

For instance, the OPB_SysAce module, SysACE_MPA bus is defined in the MPD with the ordering:

SysACE_MPA = "", DIR= OUT, VEC=[6:0]

So starting in version 6.1, the MHS global port VEC ordering should match this. For instance:


To work around this issue, change the VEC notation in the MHS so that it matches the MPD.

This problem will be addressed in future releases of the tools.
AR# 18559
Date Created 12/05/2003
Last Updated 04/09/2007
Status Archive
Type General Article