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AR# 18562

Platform Flash PROM (XCF08P/XCF16P/XCF32P) Errata - Programming and verification failures occur when I target XCFxxP PROM engineering samples

Description

Keywords: XCF, 8, 16, 32, iMPACT, fail, program, config, verify, readback, TCK, issues

Urgency: Standard

General Description:
Programming and verification failures occur when I target XCFxxP PROM engineering samples. To successfully program and readback/verify, XCFxxP PROM engineering samples, TCK must be greater than 3 MHz. More information on this issue is available in the "Platform Flash XCF08P/XCF16P/XCF32P PROM Engineering Sample Errata". Please see (Xilinx Answer 18815) for details on accessing Xilinx errata.

Solution

Always use the latest version of iMPACT with a Parallel Cable IV cable running at 5 MHz (ECP mode) to successfully program and verify the PROM. All known engineering sample issues are documented in the Platform Flash PROM Engineering Sample errata. These issues include the following:

NOTE: These issues affect only the XCF08P, XCF16P, and XCF32P PROM early engineering samples marked with "ES". It is corrected in the later engineering samples marked with "ESB". These issues do NOT affect the XCF01S, XCF02S, or XCF04S PROMs.

1. TCK must be greater than 3 MHz to successfully program and verify the PROM via JTAG.
2. The FPGA may not complete the startup sequence correctly if the PROM's CLK_OUT is used to clock the configuration sequence. This does not affect configuration when the FPGA is in Master Serial mode or Master SelectMAP mode, or when the configuration sequence is clocked by an external oscillator.
3. The PROM's decompressor is not enabled.
4. The PROM may not issue correct data for free-running CLK source.
AR# 18562
Date Created 12/05/2003
Last Updated 02/10/2007
Status Archive
Type General Article