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AR# 18569

6.1i HDL Bencher - When creating a new tbw file, I get the following error: ERRORS while extracting ports, please check the syntax of the <file>.vhd

Description

Keywords: HDL Bencher, types, VHDL, 4.2i, testbench, package

Urgency: Standard

General Description:
When I try to create a new tbw file I get the error message:

ERRORS while extracting ports, please check the syntax of the <file>.vhd

Solution

1

One reason why this can happen is if the user has a package that uses a non-standard data type.

If there are data types in a package file that is not std_logic or std_logic_vector, then this problem can occur.

2

This error can occur if unrecognized synthesis attributes are used in the code such as the following:

library synplify;
use synplify.attributes.all;

removing the line with the attributes eliminates the problem and allows you to create a testbench.

This problem is fixed in ISE 7.1i
AR# 18569
Date Created 12/08/2003
Last Updated 06/09/2009
Status Archive
Type General Article