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AR# 18576

12.1 Known Issue - Timing Analyzer, TRACE - Different data valid windows for a differential input can be calculated based on the information given in the data sheet section of the Timing report

Description

My design contains LVDS signal and implements a DDR application. When I look into the Data Sheet section of the timing report, and calculate the data valid window for my input, I find two different values. 

 

Setup/Hold to clock up_rx_clk_p 

---------------+------------+------------+------------------+--------+ 

.......................... | Setup to | Hold to | ................................ | Clock | 

Source...............| clk (edge) | clk (edge) |Internal Clock(s) .....| Phase | 

----------------------------------------------+------------+------------+------------------+--------+ 

up_rx_dat_p<0> | 0.179(R)| 1.222(R)|up_rx_clk_180_buf | 1.500| 

...........................| 1.654(R)| -0.247(R)|up_rx_clk_0_buf | 0.000| 

 

 

Why are the resulting data valid windows different for the differential input?

Solution

The data and clock delays should be the same for both the CLK0 and CLK180. 

 

Although the setup and hold times are different, because of phase differences between CLK0 and CLK180, the data valid window for a given differential input should be identical.

AR# 18576
Date Created 09/03/2007
Last Updated 05/16/2014
Status Archive
Type General Article