AR #18579 - 9.1i Timing - Different setup time reported in Setup/Hold table for differential input

Description

Keywords: ISE6.1, Trace, differential, LVDS,DDR, data sheet, analysis

In a DDR design, using LVDS signaling for the same input, I can see different setup values reported in the setup/hold tables of the data sheet section of the timing report.

Setup/Hold to clock user_rx_clk_n
------------------------------+------------+------------+------------------+--------+
.............................| Setup to | Hold to |........................... | Clock |
Source..................| clk (edge) | clk (edge) |Internal Clock(s) | Phase |
------------------------------+------------+------------+------------------+--------+
user_rx_dat_p<0> | 0.676(R)| 1.222(R)|user_rx_clk_180_buf | 1.500|
.............................| 2.151(R)| -0.247(R)|user_rx_clk_0_buf.....| 0.000|

Setup/Hold to clock user_rx_clk_p
-------------------------------+------------+------------+------------------+--------+
................................| Setup to | Hold to |........................... | Clock |
Source.....................| clk (edge) | clk (edge) |Internal Clock(s) | Phase |
--------------------------------+------------+------------+------------------+--------+
user_rx_dat_p<0>....| 0.179(R)| 1.222(R)|user_rx_clk_180_buf | 1.500|
................................| 1.654(R)| -0.247(R)|user_rx_clk_0_buf | 0.000|


Should the setup value be the same for both sides of the clock?