9.1i Timing - Different setup time reported in Setup/Hold table for differential input

Description

In a DDR design, using LVDS signaling for the same input, I can see different setup values reported in the setup/hold tables of the data sheet section of the timing report.  

Setup/Hold to clock user_rx_clk_n 

------------------------------+------------+------------+------------------+--------+ 

.............................| Setup to | Hold to |........................... | Clock | 

Source..................| clk (edge) | clk (edge) |Internal Clock(s) | Phase | 

------------------------------+------------+------------+------------------+--------+ 

user_rx_dat_p<0> | 0.676(R)| 1.222(R)|user_rx_clk_180_buf | 1.500| 

.............................| 2.151(R)| -0.247(R)|user_rx_clk_0_buf.....| 0.000| 

Setup/Hold to clock user_rx_clk_p 

-------------------------------+------------+------------+------------------+--------+ 

................................| Setup to | Hold to |........................... | Clock | 

Source.....................| clk (edge) | clk (edge) |Internal Clock(s) | Phase | 

--------------------------------+------------+------------+------------------+--------+ 

user_rx_dat_p<0>....| 0.179(R)| 1.222(R)|user_rx_clk_180_buf | 1.500| 

................................| 1.654(R)| -0.247(R)|user_rx_clk_0_buf | 0.000| 

Should the setup value be the same for both sides of the clock?

Solution

The setup/hold tables for both the P and N side of the clock should be the same. 

To work around this issue, take the P side of the Clock as a reference for timing analysis.

This problem has been fixed in the latest 8.1i Service Pack available at: 

http://www.xilinx.com/xlnx/xil_sw_updates_home.jsp
The first service pack containing the fix is 8.1i Service Pack 1.