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AR# 18581

LogiCORE SPI-4.2 Lite (POS-PHY L4) v2.0 - RTL simulation generates error: "Timing Violation Error : FINE_SHIFT_RANGE on instance exceeds 10.000 ns. PHASE_SHIFT * PERIOD / 256 = -255"

Description

General Description: 

When I attempt a RTL (Post Translate) simulation with the SPI4.2 Lite v2.0 core, the simulator issues the following error message: 

 

"Timing Violation Error : FINE_SHIFT_RANGE on instance exceeds 10.000 ns. PHASE_SHIFT * PERIOD / 256 = -255 * 11.424 / 256 = 72057402375023.734." 

 

Why does this happen?

Solution

To work around this issue, make the following changes: 

 

VHDL  

 

Sink Core 

 

RTL Simulation:  

 

1. Open the pl4_lite_snk_top.vhd file. 

2. Search for X_DCM. 

3. Make the following changes to the PHASE_SHIFT: 

 

pl4_snk_clk0_rdclk_dcm0 : X_DCM 

generic map( 

DLL_FREQUENCY_MODE => "LOW", 

CLK_FEEDBACK => "1X", 

CLKOUT_PHASE_SHIFT => "FIXED", 

PHASE_SHIFT => 62, 

DESKEW_ADJUST => "SOURCE_SYNCHRONOUS" 

 

UCF: 

 

No changes are needed. 

 

Source Core 

 

RTL Simulation:  

 

1. Open the pl4_lite_src_top_master_addr.vhd file. 

2. Search for X_DCM. 

3. Make the following changes to the PHASE_SHIFT: 

 

pl4_lite_src_clk0_tdclk_dcm0 : X_DCM 

generic map( 

DLL_FREQUENCY_MODE => "LOW", 

CLK_FEEDBACK => "1X", 

CLKOUT_PHASE_SHIFT => "FIXED", 

PHASE_SHIFT => 0, 

DESKEW_ADJUST => "SOURCE_SYNCHRONOUS" 

 

UCF: 

 

Add the following line: 

 

INST "pl4_lite_src_top0/pl4_lite_src_clk0/tdclk_dcm0" PHASE_SHIFT = 0;  

 

NOTE: See Resolution 2 for the Verilog solution.

 

Verilog  

 

Sink Core 

 

RTL Simulation:  

 

1. Open the "pl4_lite_snk_top.v" file.  

2. Search for X_DCM. 

3. Make the following changes to the PHASE_SHIFT: 

 

defparam \pl4_snk_clk0/rdclk_dcm0 .DLL_FREQUENCY_MODE = "LOW"; 

defparam \pl4_snk_clk0/rdclk_dcm0 .CLK_FEEDBACK = "1X"; 

defparam \pl4_snk_clk0/rdclk_dcm0 .CLKOUT_PHASE_SHIFT = "FIXED"; 

defparam \pl4_snk_clk0/rdclk_dcm0 .PHASE_SHIFT = 62; 

defparam \pl4_snk_clk0/rdclk_dcm0 .DESKEW_ADJUST = "SOURCE_SYNCHRONOUS"; 

X_DCM \pl4_snk_clk0/rdclk_dcm0 ( 

 

UCF: 

 

No changes are needed. 

 

Source Core 

 

RTL Simulation:  

1. Open the "pl4_lite_src_top_master_addr.v" file. 

2. Search for X_DCM. 

3. Make the following changes to the PHASE_SHIFT: 

 

defparam \pl4_lite_src_clk0/tdclk_dcm0 .DLL_FREQUENCY_MODE = "LOW"; 

defparam \pl4_lite_src_clk0/tdclk_dcm0 .CLK_FEEDBACK = "1X"; 

defparam \pl4_lite_src_clk0/tdclk_dcm0 .CLKOUT_PHASE_SHIFT = "FIXED"; 

defparam \pl4_lite_src_clk0/tdclk_dcm0 .PHASE_SHIFT = 0; 

defparam \pl4_lite_src_clk0/tdclk_dcm0 .DESKEW_ADJUST = "SOURCE_SYNCHRONOUS"; 

X_DCM \pl4_lite_src_clk0/tdclk_dcm0 ( 

 

UCF: 

 

Add the following line: 

 

INST "pl4_lite_src_top0/pl4_lite_src_clk0/tdclk_dcm0" PHASE_SHIFT = 0;  

 

NOTE: This problem will be corrected in the version 2.0.1 release of the core.

AR# 18581
Date Created 09/03/2007
Last Updated 05/16/2014
Status Archive
Type General Article