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AR# 18622

6.1i Core Generator IP Update #1 (G_ip1) - Known Issues for System Logic IP


General Description:

This Answer Record contains Known Issues regarding System Logic IP released with 6.1i IP Update #1 (aka G_ip1).


LogiCORE Asynchronous FIFO v5.1: Unable to generate async FIFO with FIFO depth anything other than 15. Also, generating async FIFO with type=Dist memory causes the CORE Generation to hang and the need to kill CORE Generator from the task bar.

Please see (Xilinx Answer 18708).

LogiCORE Linear Feedback Shift Register v2.0: "ERROR: Unable to customize core Linear Feedback Shift Register." After installing 6.1i IP Update #1 (G_ip1), and adding the LFSR v2.0 from the Cores Catalog, I cannot open the LFSR v2.0 GUI.

Please see (Xilinx Answer 18620).

LogiCORE Bit MUX v7.0- MAP error: "ERROR: Pack:1141 wide function starting with F6 MUX." When running MAP phase of implementation, you might get a MAP error if your design contains CORE Generator Bit MUX v7.0 that contains RPM. This is known to occur on Virtex-II, Virtex-II Pro, and Spartan-3 designs.

Please see (Xilinx Answer 18621).
AR# 18622
Date Created 09/03/2007
Last Updated 07/28/2010
Status Archive
Type General Article