We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 18666

5.1i/6.1i COREGen Bus Mux V6.0 - Simulating the MUX_BUS Core in Verilog simulation gives incorrect results


General Description: 
When the C_MUX_BUS_V6 Core is used in Verilog functional simulation, the results that are produced are not functionally correct. Why is this?


The problem is in the Verilog behavioral model. When using blocking statements instead of non-blocking statements, the simulation does not behave as expected. 
Open the file: 
Go to line 305 and make the following change: 
Change the lines 
if(intEN === 1'b0) 
intO = #1 `allmyZs; 
else if(intEN === 1'bx) 
intO = #1 `allmyXs;  
if(intEN === 1'b0) 
intO <= #1 `allmyZs;  
else if(intEN === 1'bx) 
intO <= #1 `allmyXs;  
This problem will be fixed in V7.0 of the core.
AR# 18666
Date Created 09/03/2007
Last Updated 05/16/2014
Status Archive
Type General Article