I have defined a clock signal in my design and placed a PERIOD constraint for that signal into the XCF.
When I synthesize my project, XST fails with an error message specifying that the signal I have defined in the XCF is not found in the design. (This occurs despite the fact that I set the option KEEP HIERARCHY in the synthesis option.)
"Mapping all equations...
Building and optimizing final netlist ...
Annotating constraints using XCF file 'Project_directory_path\try_cst.xcf'
ERROR:Xst:1370 - Line 11: Signal name clock_signal_name not found in design.
ERROR:Parsers:11 - Encountered unrecognized constraint while parsing.
ERROR:Xst:1341 - XCF parsing failed"
How can I solve this problem?
This problem occurs when the clock signal is connected to an output PAD of the FPGA. XST will automatically replace the clock net name in your design with the name associated to the PAD.
To prevent XST from changing the name of the clock signal, modify your code by placing a KEEP attribute on the clock signal.
This can done by adding the following lines in your code:
Declare the KEEP attribute in your file architecture, before the "begin" keyword:
attribute keep : string;
After KEEP and your clock signal have been declared, specify the VHDL constraint as follows:
attribute keep of clock_signal_name: signal is "true";
// synthesis attribute keep of clock_signal_name is true;
For more details on using the KEEP attribute, please refer to the software manual: