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AR# 18695

6.1i XST - XST generates wrong logic for the loadable counter

Description

Keywords: XST, if, elsif, else, set, reset, Behavioral, Post-translate, netlist, clear, synchronous

Urgency: Hot

General Description:
When a counter is controlled by a combination of synchronous clear, set, constant load and count enable in the same process, the behavioral simulation is different from the Post-Translate simulation indicating that XST produced incorrect logic during synthesis.
Wrong Example.
=======================================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
-- library UNISIM;
-- use UNISIM.VComponents.all;

entity TOP_TEST_COUNT is
Port ( CLK : in std_logic;
R_RST : in std_logic;
D_VALID_VZ : in std_logic_vector(1 downto 0);
SET_R_COUNT : in std_logic;
SET_R_COUNT_VALUE : in std_logic_vector(1 downto 0);
R_COUNT_OUT : out std_logic_vector(3 downto 0));
end TOP_TEST_COUNT;

architecture Behavioral of TOP_TEST_COUNT is

signal r_count : std_logic_vector(3 downto 0);

begin

process (CLK)
begin
if rising_edge(CLK) then
if R_RST ='1'then
r_count <= "0000";
else
if set_r_count = '1' then
case set_r_count_value is
when "11"
=> r_count <= "0011";
when "10"
=> r_count <= "0010";
when "01"
=> r_count <= "0001";
when others
=> r_count <= "0000";
end case;
else
if r_count = "1000" and d_valid_vz = "10" then
r_count <= "0000";
elsif r_count >= "1001" and d_valid_vz = "01" then
r_count <= "0000";
elsif r_count >= "1001" and d_valid_vz = "10" then
r_count <= "0001";
else
r_count <= r_count + d_valid_vz;
end if;
end if;
end if;
end if;
end process;


R_COUNT_OUT <= r_count;

end Behavioral;


=======================================================================================

Solution

To solve the problem, the work-around is to put the control signal in two separate combinatorial processes.
and the counter in a clock process.

===================================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
-- library UNISIM;
-- use UNISIM.VComponents.all;

entity TOP_TEST_COUNT is
Port ( CLK : in std_logic;
R_RST : in std_logic;
D_VALID_VZ : in std_logic_vector(1 downto 0);
SET_R_COUNT : in std_logic;
SET_R_COUNT_VALUE : in std_logic_vector(1 downto 0);
R_COUNT_OUT : out std_logic_vector(3 downto 0));
end TOP_TEST_COUNT;

architecture Behavioral of TOP_TEST_COUNT is

signal r_count : std_logic_vector(3 downto 0);

signal xgr1, xgr2: std_logic_vector(3 downto 0);

begin


process (set_r_count_value)
begin
case set_r_count_value is
when "11" => xgr1 <= "0011";
when "10" => xgr1 <= "0010";
when "01" => xgr1 <= "0001";
when others => xgr1 <= "0000";
end case;

end process;

process (r_count, d_valid_vz)
begin
if r_count = "1000" and d_valid_vz = "10" then xgr2 <= "0000";
elsif r_count >= "1001" and d_valid_vz = "01" then xgr2 <= "0000";
elsif r_count >= "1001" and d_valid_vz = "10" then xgr2 <= "0001";
else xgr2 <= r_count + d_valid_vz;
end if;

end process;


process (CLK)
begin
if rising_edge(CLK) then
if R_RST ='1'then
r_count <= "0000";
else
if set_r_count = '1' then
r_count <= xgr1;
else
r_count <= xgr2;
end if;
end if;
end if;
end process;


R_COUNT_OUT <= r_count;

end Behavioral;

=========================================================================================

AR# 18695
Date Created 12/23/2003
Last Updated 03/07/2006
Status Archive
Type General Article