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AR# 18797

6.2i CPLD FPGA Timing Simulation - "Vsim - instance does not have generic named 'tperiod_clk_posedge', failed to find matching specify timing constraint"

Description

General Description:

When performing a timing simulation, I receive error messages similar to the following:

VHDL

"** Error: (vsim-SDF-3240) watch_timesim.sdf(361): Instance '/uut/lsbcnt_0_mc_reg' does not have a generic named 'tperiod_clk_posedge'.

# ** Error: (vsim-SDF-3240) watch_timesim.sdf(1792): Instance '/uut/lsbcnt_1_mc_reg' does not have a generic named 'tperiod_clk_posedge'.

# Error loading design."

Verilog

"# ** Error: (vsim-SDF-3262) watch_timesim.sdf(377): Failed to find matching specify timing constraint.

# ** Error: (vsim-SDF-3262) watch_timesim.sdf(491): Failed to find matching specify timing constraint.

# ** Fatal: (vsim-SDF-3445) Failed to parse SDF file 'watch_timesim.sdf'."

Solution

If upgrading from 6.1i to 6.2i, please also update the simulation libraries. These libraries are already compiled if you obtain the latest version of ModelSim MXE. At the time of 6.2i release, the latest version was 5.7g.

For more information on obtaining or upgrading ModelSim simulation libraries, please see (Xilinx Answer 2561).

If the design is targeting a CoolRunner-II device with dual-edge registers, these errors are due to a bug in the timing netlist.

This problem has been fixed in the latest 6.2i Service Pack, available at:

http://support.xilinx.com/xlnx/xil_sw_updates_home.jsp
The first service pack containing the fix is 6.2i Service Pack 1.

AR# 18797
Date Created 09/03/2007
Last Updated 12/15/2012
Status Active
Type General Article