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AR# 18804

6.2 / 6.1 EDK - How do I define my interrupt priorities using OPB_INTC/DCR_INTC controllers?


Keywords: INTC, interrupt, priority, XPS, Intr

Urgency: Standard

General Description:
How do I define my interrupt priorities using OPB_INTC/DCR_INTC in my MHS file?


The Intr port is an input vector to the OPB_INTC/DCR_INTC controller, collecting interrupt sources from other peripherals or external pins. Its width is defined by the parameter C_NUM_INTR_INPUTS.

In EDK, PlatGen will calculate the number of interrupt signals connecting to the Intr port and automatically assign the value of C_NUM_INTR_INPUTS of the interrupt controller. Users need not assign any value in this case. Also notice that unlike other CoreConnect bus signals, the bit notation for Intr is little endian [C_NUM_INTR_INPUTS-1 downto 0].

It is interesting to note that the interrupt priority is not a syntax defined in MHS, but rather depends on how the interrupt controllers are implemented. Xilinx's OPB_INT/DCR_INTC controllers define this interrupt source priority. The LSB of the Intr bus has the highest priority, and the interrupts that are connected to the MSB have the lowest priority.

The following is the example for MHS syntax for the current interrupt controllers:

BEGIN opb_intc
Port Intr = uart_int & iic_int & ext_int & emac_int

In this case, PlatGen will automatically calculate C_NUM_INTR_INPUTS = 4. Also, according to the concatenation syntax used in the MHS, Intr[0] will be connected to emac_int, Intr[1] will be connected to ext_int, and so on. In this example, emac_int has the highest interrupt priority since it is on the LSB position of Intr defined in OPB_INTC/DCR_INTC IPs.
AR# 18804
Date Created 01/20/2004
Last Updated 04/28/2006
Status Archive
Type General Article