We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 18825

LogiCORE xFFT v3.0 - When using the FFT in Radix 2 or Radix 4 Burst mode with start and unload signals held High, how do I detect the normal output order?


General Description: 
When using the FFT v3.0 (and 2.0 or v2.1) in Radix 2 or RADIX 4 Burst mode, I see a double DV pulse at the output of the core. In the case where the start and unload signals are asserted at the same time, there will be two DV pulses with corresponding data out on the xk_re/xk_im ports. The data coming out of the core is different for each DV pulse.


This is the expected behavior of the core. The data will first be unloaded in bit-reversed order corresponding to the first DV pulse, and then the data will be unloaded in natural order corresponding to the second DV pulse. The xk_index output of the FFT will show the order of the xk outputs. The RFD signal will be asserted during the first DV pulse, indicating that the memory is free to accept new data. See Page 18, Figure 13 of the v2.1 data sheet. 
If a design requires that the first bit-reversed output be ignored, you can work around the issue by doing the following: 
if ((RFD='0') and (DV='1')) 
my_data_valid= true; 
my_data_valid= false; 
if ((RFD == 0) and (DV == 1)) 
my_data_valid = true; 
my_data_valid = false;
AR# 18825
Date Created 09/03/2007
Last Updated 05/16/2014
Status Archive
Type General Article