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AR# 18834

Virtex-II - Speeds Files Revision History

Description

What is the speeds files revision history for the Virtex-II device family?

Solution

Speeds Files Revision History

1.121 Release: Description and Explanation of Changes

- New I/O Standards support is added.

1.120 Release: Description and Explanation of Changes

- Speed grade designators are changed to PRODUCTION for Hi-Rel and radiation-hardened devices.

1.119 Release: Description and Explanation of Changes

- Support is added for HSLVDCI_{15,18,25,33} I/O adjustment.

1.118 Release: Description and Explanation of Changes

- No major changes to the values.

- Support is added for Hi-Rel and radiation-hardened devices.

1.116 Release: Description and Explanation of Changes

- The new output delays for each speed grade are reduced by the following amounts:

Speed Grade..................-4..............-5..............-6

Output Delay Change....-1.12ns...-1.1ns....-1.0ns

- No change to the silicon; this is strictly a specification I/O number change from TRCE for all I/O standards improved.

- You must account for board-loading separately.

1.114 Release: Description and Explanation of Changes

- I/O adjustments are updated (based on measurements made with "0" load).

- Voltage and temperature de-rating data are included.

- Values for TICKOF and TPSFD/TPHFD for 2V8000 devices are corrected.

1.113 Release: Description and Explanation of Changes

- The positive hold times specification is rolled back to "0" for 2V2000, 2V3000, and 2V4000 devices.

- HLL/VLL delays are adjusted for -6.

- Stepping 0 -6 multiplier set is equal to Stepping 1 -6 multiplier speeds.

- Minimum delays are supported.

- v1.113 is identical to v1.111. For more information on v1.111, see below.

NOTE: From (Xilinx Answer 15576).

1.111 Release: Description and Explanation of Changes

- TPHFD for XC2V2000, XC2V3000, and XC2V4000 devices is changed to "0" from a positive value for the -4 speed grade.

- Horizontal and vertical long line delays are adjusted for the -6 speed grade.

- The stepping level 0 for the -6 speed grade for multipliers is set equal to Stepping Level 1.

- Support for MINs is available.

NOTE: From (Xilinx Answer 15218).

1.105 Release: Description and Explanation of Changes

-The XC2V80, XC2V250, XC2V500, XC2V2000, XC2V3000, and XC2V4000 devices are designated production devices for -4 and -5 speed grades.

- Multiplier performance is greatly improved for the stepping-one multiplier design. These numbers are reflected in the "Enhanced Multiplier" section of the data sheet, which is available at:

http://www.xilinx.com/xlnx/xweb/xil_publications_index.jsp
- Select "Virtex-II" under "FPGA Device Families."

- Select "Virtex-II DC and Switching Characteristics" (Module 3).

- Go to the "Virtex-II Switching Characteristics" section and select "Enhanced Multiplier Switching Characteristics."

- BRAM dedicated address routing delay is increased.

- The "HEX/LongLine" routing delay was adjusted on XC2V80, XC2V250, and XC2V500 devices.

- Pin-to-pin parameter with delay (Tpsfd/Tphfd) changes are made, as reflected in the above data sheet.

- Changes in the adjustment factors for I/O standards other than LVTTL are made, as reflected in the above data sheet.

NOTE: From (Xilinx Answer 15218).

1.96 Release: Description and Explanation of Changes

- Longline delays have increased.

- The values for the multiplier have changed to accurately reflect lower order multiplication functions (less than 18-bit multiplication). The worst case (Tmult_P35) did not become worse.

- Pipelined-multiplier setup times (data path) have increased.

- The 2V6000 device is now at production level for -5 and -4 speed grades.

1.94 Release: Description and Explanation of Changes

- This release reverts back to version 1.89 pin-to-pin numbers. (Data sheet Module 3, Revision 1.6).

- Multiplier Changes:

18X18 combinatorial multiplier

Speeds Files Release...Parameter....-6.......-5.......-4

Ver. 1.89.....................Tmult_P35....N/A.....6.40ns...7.38ns

Ver. 1.90.....................Tmult_P35....5.6ns...7.1ns....8.1ns

Ver. 1.94.....................Tmult_P35....6.44ns..8.48ns...10.40ns

- Certain output I/O standard adjustments have changed; all have been verified and reflect characterization data.

- HSTL (Class 1 through 4) 1.8 V has been added to the data sheet with adjustment values.

1.90 Release: Description and Explanation of Changes

Multiplier:

- The Pipelined model is fixed.

- There is now a constant set-up across input pins.

- CLK2OUT is now ~80% of nonpipelined multiplier delay (was ~50%).

- There is a 10% increase to nonpipelined delays.

- Delay depends on the operands to the multiplier.

- "Worst" test case, measured on silicon, shows ~7.0ns for an 18X18 multiplier.

- Delays reflect production silicon.

- For 2V1000 devices, -4 and -5 speed grades are changed to "production."

- For all other parts, speeds grades remain advanced.

- A -6 speed grade is added (not available for 2V8000 devices); this is ~10% faster than -5 for most delays; the 18X18 delay is ~5.6ns for -6 compared to 7ns for -5.

- Tbcko BRAM CLK2OUT increases from 2.0ns to a 2.26ns; a delay is transferred from routing on the CLK pin to the BRAM block, but this should not affect design performance.

- Internal hold times on flip-flops, BRAM are set to "0" (were "1" ps).

- I/O adjustment factors are updated based on production silicon.

Definitions

For definitions of the speed file designation per device size and speed grade, refer to the "DC and Switching Characteristics" data sheet at:

http://www.xilinx.com/xlnx/xweb/xil_publications_index.jsp
- Select "Virtex-II" under "FPGA Device Families."

- Select "Virtex-II DC" and "Switching Characteristics (Module 3)."

For information on the current speeds file versions with respect to design tool releases, please see (Xilinx Answer 12201).

AR# 18834
Date Created 09/03/2007
Last Updated 12/15/2012
Status Active
Type General Article