This Answer Record contains the Release Notes for SPI-4.2, also known as POS-PHY Level 4 (PL4) version 6.2, and includes the following:
- Software Requirements
- What's New in SPI-4.2 v6.2
- Supported Device/Package Information
- Known Issues
The Xilinx 6.3i CORE Generator (included with the ISE 6.3i software) is required to generate the SPI-4.2 v6.2 Core. Additionally, the latest service packs and IP updates must be installed prior to installing the "spi4_2_v6_2.zip" or "spi4_2_v6_2.tar.gz."
The recommended order of installation is as follows:
1. ISE 6.3i CD
2. ISE 6.3i Service Pack 2 or the latest Service Pack
3. ISE 6.3i IP Update 4 or the latest update
4. "spi4_2_v6_2.zip" or "spi4_2_v6_2.tar.gz" (available only to PL4 customers)
NOTE: If you are still using ISE 6.2i or ISE 6.1i, it is recommended that you upgrade to ISE 6.3i before installing SPI4.2 v6.2 Core. ISE 6.3i CD are shipped to all the registered ISE customers. If you cannot upgrade to ISE 6.3i, please contact the Xilinx hotline to obtain SPI4.2 v6.1.
SPI4.2 Core and ISE S/W compatibility:
SPI4.2 v6.1: compatible with ISE 6.1i or 6.2i , supporting Virtex-II, Virtex-II Pro
SPI4.2 v6.2: compatible with ISE 6.3i, supporting Virtex-II, Virtex-II Pro
SPI4.2 v7.1: compatible with ISE 6.3i, supporting Virtex-4
Software Service Packs are available at:
The latest ISE 6.3i IP Update is available at:
Same link as Software Service Pack page. Select IP Update for the update type.
"spi4_2_v6_2.zip" or "spi4_2_v6_2.tar.gz" is available (for PL4 customers only) at:
What's New in SPI4.2 v6.2
SPI4.2 v6.2 Core contains the same feature as v6.1 Core; however, it is now compatible with ISE 6.3i. The general features, Source core features, Sink core features, and device - package support are the same as v6.1 Core. The list of known issues for v6.1 also applies to v6.2 Core.
- A selectable 128-bit user interface is available for all devices/packages supported
- Expanded dual-core solutions
- Expanded device/package support
- A new configurable Verilog demo testbench
- Complete data burst transmitted when the Source core is out of frame
- A diagnostic tool that enables the forced insertion of DIP2 errors
- Improved error handling with the new SnkBusErrStat[7:0] signal
Supported Device and Package Information for SPI4.2 v6.1 and v6.2
Please see (Xilinx Answer 12420) for a list of SPI-4.2 (PL4) Known Issues.