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AR# 18901

LogiCORE 32 pt FFT v3.0 - Why does the output data appear to be shifted when reading the output from xk_re and xk_im?

Description

Keywords: CORE Generator, known, issues, output, FFT, xk_re, xk_im

Why does the output data appear to be shifted when reading the output from xk_re and xk_im?

Solution

The output data appears to be shifted because it takes one clock cycle for the MRD to be registered, and for the block RAM to start outputing data. Figure 7 (Single-Memory-Space configuration - result read timing) in the "High-Performance 32-Point Complex FFT/IFFT V3.0" data sheet should have one clock cycle between MRD toggle and the XK output. To access the data sheet, click on the following link and select Data Sheet under Product Details:
http://www.xilinx.com/xlnx/xebiz/designResources/ip_product_details.jsp?sGlobalNavPick=PRODUCTS&sSecondaryNavPick=Design+Tools&category=&iLanguageID=1&key=32FFT

If you need an example, please contact the Xilinx Technical Support and provide the answers to the questions below:
http://support.xilinx.com/support/services/contact_info.htm

Target part or family?
Target application?
FFT point size?
Data Bit widths?
Twiddle Factor Bit widths?
Sample rate?
Clock rate?


AR# 18901
Date Created 09/03/2007
Last Updated 09/10/2008
Status Archive
Type General Article