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AR# 18902

LogiCORE SPI-4.2 (POS-PHY L4) v6.0 - List of all Known Issues for PL4 v6.0/6.0.1

Description

General Description: 

This Answer Record contains a list of all known issues for SPI-4.2, also known as POS-PHY Level 4 (PL4) v6.0 and v6.0.1.  

 

The list is divided into the following sections: 

- Constraints and Implementation 

- Simulation 

- Hardware 

- Other Helpful Answer Records 

 

The SPI-4.2 v6.0.1 core contains minor upgrades to v6.0. Most of the issues mentioned below for v6.0 still apply to v6.0.1. However, the following issues have been updated: 

 

1. The SPI-4.2 v6.0 GUI points to the v5.2 data sheet when I click "DATA SHEET". The v6.0.1 GUI now points to the v6.0.1 (the latest) data sheet. 

2. Dynamic Phase Alignment Sink core might not go in-frame due to a missing timing constraint. See (Xilinx Answer 18167). This issue has been fixed in SPI-4.2 v6.0.1. 

3. Virtex-II Pro: The "Use inverted CLK0 to generate CLK180" option has been removed from the Sink core GUI.

Solution

V6.0 SPI-4.2 KNOWN ISSUES 

 

Constraints and Implementation 

- SPI-4.2 v6.0.x release is fully tested and supported to work with ISE 5.2i SP3, 5.2i IP Update 2. It has not been tested with ISE 5.1i or ISE 6.1i. Please see (Xilinx Answer 18500) for possible work-arounds. 

- SPI-4.2 signals are locked to specific I/O locations. Altering these pin locations is NOT recommended. See (Xilinx Answer 18087)

- SPI-4.2 signals default to LVDS without the internal device termination. If internal termination is desired, then you must set this in the UCF file. See (Xilinx Answer 18089)

- Speed files patches are needed to implement SPI-4.2 v6.0 designs. See (Xilinx Answer 17687)

- Migrating SPI-4.2 core from v5.2 to v6. See (Xilinx Answer 17800)

- RDClk_P pinout constraint of 2VP30-FF1152 (East or Bank 2 and 3) generated by Core Generator is different than SPW's pinout. See (Xilinx Answer 18316)

- SPI-4.2 v6.0 GUI still points to the v5.2 data sheet when I click "DATA SHEET". Please use the v6.0 data sheet located in the SPI-4.2 lounge, or use the data sheet generated by the CORE Generator when you generate the SPI-4.2 core. The file will be created in your CORE Generator project directory: 

"../<core_name>/doc/spi4_2_v6_product_spec.pdf". This issue is addressed in SPI-4.2 v6.0.1. 

- Does the SPI-4.2 (PL4) core have a required startup sequence or reset procedure? See (Xilinx Answer 16176)

- When I run the ISE 5.2i implementation tool with an SPI-4.2 (PL4) core, several NGDBuild warning messages are reported. See (Xilinx Answer 17764).  

- When I run the ISE 5.2i Place and Route tool (PAR) with an SPI-4.2 (PL4) core, many timing errors are reported. See (Xilinx Answer 16540).  

- When using SPI-4.2 v6.0 sink core, I see improper concatenation of the packets when SOP spacing is violated and if the first packet is not terminated properly with EOP. See (Xilinx Answer 17690)

- When using SPI-4.2 v6.0 source core with SrcBurstMode=1, and the source core goes out of frame, it begins transmitting training patterns on the credit boundary, not the burst boundary. This violates the premise of the Burst FIFO (though it does not violate the SPI-4.2 specification). The correct behavior is to send the training on the burst boundary. See (Xilinx Answer 17691)

- When I use the SPI-4.2 v6.0 core, SnkFFPayloadDIP4 is not asserted when the packet size is less than two bytes. See (Xilinx Answer 17692)

- When an SPI-4.2 (PL4) core is generated through CORE Generator, the following errors occur: 

"ERROR:Failure to create .sym symbol file. Cannot post process ASY symbol file. File C:\test\5_2i\pl4_core.asy does not exist." 

"ERROR: Did not generate ISE symbol file for core <pl4_core>." 

See (Xilinx Answer 15493)

 

Simulation 

- When simulating a SPI-4.2 (PL4) source core, glitches occur on TDat and TCtl. This is visible on gate-level simulation as well as in timing simulation. See (Xilinx Answer 15579)

- When simulating the SPI-4.2 core, an unknown state or "x" appears on RStat along with setup and hold time violations. See (Xilinx Answer 17686)

- Simulation of the SPI-4.2 (PL4) core using dynamic alignment requires timing simulation to properly simulate the dynamic alignment per-bit de-skew capabilities of the Sink core. See (Xilinx Answer 15436)

- When I simulate an SPI-4.2 (PL4) core using NC-Verilog (by Cadence) or VCS (by Synopsys), unusual and inconsistent behaviors occur. See (Xilinx Answer 15578)

 

Hardware  

- When Fixed Static Alignment is used, it is necessary to determine the best DCM setting (PHASE SHIFT) to ensure that the target system contains the maximum system margin and performs across voltage, temperature, and process (multiple chips) variations. See (Xilinx Answer 16112)

- An SPI-4.2 (PL4) Sink core with dynamic alignment fails to activate PhaseAlignComplete, goes out of sync, or reports a DIP4 error. See (Xilinx Answer 15442)

- Virtex-II Pro Static Alignment: Your design might not function properly if you are using SPI-4.2 option "Use inverted CLK0 to generate CLK180" for the Sink core. This option has been removed from SPI-4.2 v6.0.1 GUI. If you have been using this option for Virtex-II Pro, please open a WebCase at: 

http://support.xilinx.com/support/clearexpress/websupport.htm
and have the case escalated to Virtex-II Pro or SPI-4.2 experts. 

- Dynamic Phase Alignment Sink core might not go in-frame due to a missing timing constraint. See (Xilinx Answer 18167). This issue has been fixed in SPI-4.2 v6.0.1. 

 

Other Helpful Answer Records 

- What is the power consumption of the v6.0 SPI-4.2 (PL4) core? See (Xilinx Answer 16034)

- Is there a description of error and control signals in addition to the information provided in the SPI-4.2 (PL4) data sheet? See (Xilinx Answer 14968)

- How do I edit the SPI-4.2 (PL4) UCF file so that the TSClk is skewed by 180 degrees in the DCM? See (Xilinx Answer 15500)

 

SPI- 4.2 (PL4) v5.2 KNOWN ISSUES 

The PL4 v5.2 core is now obsolete. Please upgrade to the latest version of the core. See (Xilinx Answer 17664) for information on existing PL4 v5.0 issues. 

 

SPI- 4.2 (PL4) v5.0 KNOWN ISSUES 

The PL4 v5.0 core is now obsolete. Please upgrade to the latest version of the core. See (Xilinx Answer 16546) for information on existing PL4 v5.0 issues. 

 

SPI- 4.2 (PL4) v4.0 KNOWN ISSUES 

The PL4 v4.0 core is now obsolete. Please upgrade to the latest version of the core. See (Xilinx Answer 16331) for information on existing PL4 v4.0 issues. 

 

SPI-4.2 (PL4) v3.x KNOWN ISSUES  

The PL4 v3.x is no longer supported for new customers; please use the latest version of the core. See (Xilinx Answer 16332) for information on existing PL4 v3.x issues.

AR# 18902
Date Created 09/03/2007
Last Updated 05/16/2014
Status Archive
Type General Article