We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 18920

LogiCORE PCI Express - Core will not train, returning TS2 with LINK=0 and LANE=0 instead of TS1 with LINK=0 and LANE=PAD



General Description:

PCI Express core is plugged into a Motherboard, but is not training properly.

A clue will be that after sending a downstream TS1 ordered set with the LINK=0 and LANE=PAD, the core returns an upstream TS2 ordered set with LINK = 0 and LANE = 0. The upstream packet should have been a TS1 ordered set with LINK=0 and LANE=PAD.


Check the configuration file and make sure bit 511 is set to a 0. When the core is communicating with a root complex or switch, this is the setting to use:

assign cfg[510] = 1'b0;

The "two PLM autoconfigure" option allows two endpoint cores to be connected in a point to-point configuration. In most systems, the Xilinx PCI Express Endpoint core will be the downstream device, and a Root Complex or Switch will be the upstream device. In applications where two Endpoints will communicate to each other directly, this bit must be set to a 1 for the link to train successfully.

This can be found on page 38 of the Design Guide.


AR# 18920
Date Created 09/03/2007
Last Updated 12/15/2012
Status Active
Type General Article