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AR# 18929

6.1i IP Update 1 CORE Generator - Known Issues List IP-DSP

Description

This Answer Record contains known issues addressed in the 6.1i IP Update 1.

Solution

- LogiCORE CIC v3.0 

The CIC v.3 filter exhibits overflow for inputs that use the complete dynamic bit range of the data input. 

Please see (Xilinx Answer 12480)

 

- LogiCORE CORDIC v2.0 

The data sheet calculations for the Arctan example are incorrect. 

Please see (Xilinx Answer 16948)

 

- LogiCORE DA FIR Filter 

CORE Generator memory consumption with the DA FIR. 

Please see (Xilinx Answer 18663)

 

- LogiCORE DA-FIR Filter 

Calculating the clock/pipeline latency of the DA FIR filter. 

Please see (Xilinx Answer 4610)

 

- LogiCORE DA FIR Filter, MAC FIR 

Conversion from floating-point to fixed-point coefficients for Xilinx DA FIR and MAC FIR filters. 

Please see (Xilinx Answer 5366)

 

- LogiCORE DDC v1.0 

In the GUI, an error that reports an invalid parameter in the COE file is displayed in a different base format. 

Please see (Xilinx Answer 14202)

 

- LogiCORE DDC v1.0 

DDC can be implemented in the Spartan-3 and Virtex-II Pro devices. 

Please see (Xilinx Answer 18937)

 

- LogiCORE DDC v1.0 

DDC can be implemented in the Spartan-3 and Virtex-II Pro devices. 

Please see (Xilinx Answer 18937)

 

- LogiCORE DDC v1.0  

Programmable decimation implementation truncates incorrect bits. 

Please see (Xilinx Answer 19647)

 

- LogiCORE DDS v4.2 

Missing information from the data sheet for the Multi-Channel DDS operation. 

Please see (Xilinx Answer 17225)

 

- LogiCORE DDS v4.2 

Memory map information for the DDS Multi-Channel core. 

Please see (Xilinx Answer 17067)

 

- LogiCORE 32-pt Configurable FFT v3.0 

The output data appears to be in the wrong bin. 

Please see (Xilinx Answer 18901)

 

- LogiCORE 1024-pt FFTv1.0 

The block RAM configurations in the FFT/IFFT data sheet do not match the hardware configurations. 

Please see (Xilinx Answer 15311)

 

- LogiCORE 16-pt FFT v2.0 

The slice utilization of a 16-point Virtex FFT is greater than that of a 64-point FFT. 

Please see (Xilinx Answer 8765)

 

- LogiCORE 256-pt FFT v2.0 

FFT for a Virtex-II device causes PAR warnings and errors. 

Please see (Xilinx Answer 13173)

 

- LogiCORE 32-pt FFT v1.0 

No Verilog model is available for the FFT core. 

Please see (Xilinx Answer 11155)

 

- LogiCORE 64-pt FFT v2.0 

The RESULT signal is not reset properly in the 64-point FFT v2.0. 

Please see (Xilinx Answer 15383)

 

- LogiCORE FFT 

Simulation of all fixed netlist FFT (64, 256, 1024) cores generates many warnings. 

Please see (Xilinx Answer 14861)

 

- LogiCORE FFT 

Outputs connections to the fixed netlist FFT (64, 256, 1024) cores during a write operation to RAM X (TMS configuration). 

Please see (Xilinx Answer 9288)

 

- xFFT v2.1 

Radix 2 or Radix 4 Burst mode output order. 

Please see (Xilinx Answer 18825)

 

- LogiCORE MAC FIR v3.0 

Does the decimation in the MAC FIR work? 

Please see (Xilinx Answer 18589)

 

- LogiCORE MAC FIR v3.0 

Summary report does not update when changing parameters in the MAC FIR. 

Please see (Xilinx Answer 17665)

 

- LogiCORE MAC FIR v3.0 

Support for multiple MAC FIRs with different COE files in the same project. 

Please see (Xilinx Answer 16433).

AR# 18929
Date Created 09/03/2007
Last Updated 05/16/2014
Status Archive
Type General Article