" is reported.">
When I run the Verilog Demonstration Testbench, the following messages are reported:
1. "# RStat Info: Sink is out of frame. Expect TDat mismatches. <Simulation Time>"
2. "# TDat Error: Data Mismatch #4. Expected xxxx, Received xxxx. <Simulation Time>"
3. "# TDat Error: Control Mismatch: Expected x, Received x. <Simulation Time>"
When the Sink Core goes out of frame (e.g., the Sink FIFO goes almost full and static configuration signal FifoAFMode = '00'), the Demonstration Testbench immediately begins sending training without first sending an idle control word. This causes the SnkBusErr signal to assert, as a DIP4 error occurs in a training word. Additionally, the Demonstration Testbench flags errors on TDat, since data is no longer being transmitted through the core; this causes Messages #2 and #3 to be reported.
To work around these issues:
- Reduce the value of SnkAFThresAssert and SnkAFThresNegate.
- Change the value of FifoAFMode. (Re-generate the core with a modified setting in the GUI).
This problem will be addressed in a future release.