When I simulate a design with an SPI4.2 core, the following messages are reported:
"# ** Warning: /X_FF HOLD Low VIOLATION ON I WITH RESPECT TO CLK;
# Expected := 0.214 ns; Observed := 0.041 ns; At : 2929.272 ns
# Time: 2929272 ps Iteration: 3 Instance: /pl4_tstbench/pl4_top_lb0/pl4_snk_top1_pl4_snk_core0_pl4_snk_afifo0_pl4_generic_fifo0_reg_xfr_addr_gray_crossclk0_gen_reg_gray_addr_gen_reg_gray_addr_<X>_reg_gray_addr"
The timing violation is due to SPI-4.2 internal registers crossing the asynchronous clock domains. The timing violation may or may not cause the "x" unknown on the SPI4-2 core outputs. The unknown state appearing on the output signals will not affect the functionality of the core. However, in simulation, the unknown states might propagate through the design and can cause undesired effects.
If unknown states are reported during simulation, Xilinx recommends using the NGD2VHDL "-xon false" switch for VHDL simulation and the simulator switch on Verilog simulation to prevent the unknown state from propagating.
To regenerate VHDL simulation files:
prompt> ngdbuild pl4_src_top.edn
prompt> netgen -ofmt VHDL -sim -XON false pl4_src_top.ngd pl4_src_top.vhd
For Verilog, use the simulator-specific switches to turn off "x"or unknown state propagation. In this case, it would not be necessary to re-generate the simulation model.