6.1.1 System Generator for DSP - Why does VHDL generation fail when an output is connected to a scope?

Description

Keywords: SysGen, MATLAB, Simulink, scope, generation

Urgency: Standard

General Description:
Why does VHDL generation fail when an output is connected to a scope?

Example:
A design may fail to generate when a connection to a scope within his Simulink design, but with the connection broken there is no problem generating the code. There is a Fatal error with the following details reported:

Running s2x

internal error: found no driver in port list

java.lang.Exception
at com.xilinx.sysgen.a.c.a(Unknown Source)
at com.xilinx.sysgen.a.a.a(Unknown Source)
at com.xilinx.sysgen.f.h.if(Unknown Source)
at com.xilinx.sysgen.f.h.a(Unknown Source)
at com.xilinx.sysgen.b.a.e.a(Unknown Source)
at com.xilinx.sysgen.b.a.e.a(Unknown Source)
at com.xilinx.sysgen.b.g.if(Unknown Source)
at com.xilinx.sysgen.comp.b.do(Unknown Source)
at com.xilinx.sysgen.comp.b.a(Unknown Source)
at com.xilinx.sysgen.comp.GuiMain.run2(Unknown Source)
at com.xilinx.sysgen.comp.GuiMain.main(Unknown Source)

error in Simulink compiler

Solution