When trying to generate the Fibre Channel v1.0 Core in 6.2i SP3 COREGen with Verilog chosen as the Design Entry flow, an Elaboration Error might occur. Viewing the message reveals Elaboration Errors similar to the following:
"Preparing to elaborate core...
Elaborating the module...
ERROR: *** Synthesis Exception ***
The CORE Generator cannot generate the Fibre Channel Core core, core_name, as an error occurred during synthesis.
ERROR: SimGenerator: Failure of Sim to implement customization parameters core core_name
ERROR: Did not generate EDIF implementation netlist (.EDN) file for core <core_name>. Generating the .VEO/.V simulation support files..."
A problem exists with XST when the Fibre Channel Core is synthesized in the background during generation of the core within COREGen. A tactical patch has been created to fix this XST problem. This patch is necessary only for XST 6.2i Service Pack 3 as it will be fixed in the next release of the software.
Install the patch as follows:
1. Unzip the contents of the ".zip" file archive to the root directory of the Xilinx installation. Select the option that allows the extractor to overwrite all of the existing files and maintain the directory structure pre-defined in the archive.
Determine the Xilinx installation directory by entering the following at the command prompt:
UNIX or Linux
Determine the Xilinx installation directory by typing the following:
NOTE: You might need to have system administrator privileges to install the patch.
2. After installing the patch, generate the Fibre Channel v1.0 Core from the CORE Generator.