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AR# 18972

LogiCORE 10-Gigabit Ethernet MAC v4.0 - Is there an alternative method to implement the XGMII DDR clocking to reduce the number of BUFGs needed?

Description

General Description: 

When using the 10-Gigabit Ethernet MAC core with the XGMII interface, up to 7 BUFGs are needed. Is there any way to reduce the number of BUFGs necessary for the core?

Solution

When using the 10-Gigabit Ethernet MAC core with the XGMII interface on Virtex-II Pro devices, (Xilinx XAPP685): "High-Speed Clock Architecture for DDR Designs Using Local Inversion Application" can be used to implement local clock inversion, which will reduce the number of BUFG's used.  

 

http://www.xilinx.com/xlnx/xweb/xil_publications_index.jsp?category=Application+Notes
 

Note that this is applicable only to Virtex-II Pro designs.

AR# 18972
Date Created 09/03/2007
Last Updated 05/16/2014
Status Archive
Type General Article