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AR# 18992

6.2i XST - XST generates incorrect logic from a complex synchronization expression in the process


Keywords: synchronous, logic, process, VHDL, register, infer

Urgency: Standard

General Description:
XST generates incorrect logic when a complex clock expression similar to the following is used:

elsif rising_edge(wr_not) and ms_not="011" and addr="01" then


This problem has been fixed in the latest 6.2i Service Pack, available at:
The first service pack containing the fix is 6.2i Service Pack 1.

You can also solve this problem by replacing the VHDL code above with the following:
elsif rising_edge(wr_not) then
if ms_not="011" and addr="01" then
mains_on <=data(0);
AR# 18992
Date Created 02/18/2004
Last Updated 04/27/2007
Status Archive
Type General Article