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AR# 19001

6.2i ISE Install - Service Pack 3 Release Notes/README

Description

Keywords: SP1, SP2, SP3, Solaris, UNIX, PC, Linux, software, update

This README Answer Record contains the Release Notes for 6.2i Service Pack 3. The Release Notes include installation instructions and a list of the issues that are fixed by this and previous Service Packs for the 6.2i release.

Solution

1

A successful installation of Xilinx ISE 6.2i Service Pack 3 updates your software version number to 6.2.03i.

NOTES:
1. The destination directory specified during the set-up operation must contain an existing Xilinx ISE 6.2i installation. Only existing files are updated. Any new device support not previously installed should first be installed from the Xilinx ISE 6.2i CD before adding Service Pack 3.
2. You must set the Xilinx ISE 6.2i environment variable before installing Service Pack 3.

Installation Instructions for PC Users

Use one of the following methods:

Method 1
1. Download "6_2_03i_pc.exe" from:
http://www.xilinx.com/xlnx/xil_sw_updates_home.jsp
2. Run "6_2_03i_pc.exe".

Method 2
1. Establish a working Internet connection using Internet Explorer.
2. Use the WebUpdate program using one of the following methods:
- Run Start -> Programs -> ISE6 -> Accessories -> WebUpdate.
- Run "Software Updates..." (under the Help menu in Project Navigator).

Installation Instructions for Solaris Users
1. Download "6_2_03i_sol.tar.gz" from:
http://www.xilinx.com/xlnx/xil_sw_updates_home.jsp
2. Untar the downloaded file into an empty "staging" directory.

For example:
cd /home/staging_dir
gzip -d 6_2_03i_sol.tar.gz
tar xvf 6_2_03i_sol.tar

3. Run "6_2_03i_sol/setup".

Installation instructions for Linux Users
1. Download "6_2_03i_lin.tar.gz" from:
http://www.xilinx.com/xlnx/xil_sw_updates_home.jsp
2. Untar the downloaded file into an empty "staging" directory.

For example:
cd /home/staging_dir
gzip -d 6_2_03i_lin.tar.gz
tar xvf 6_2_03i_lin.tar

3. Run "6_2_03i_lin/setup".

2

Issues Fixed by 6.2i Service Packs

Architecture Wizard

(SP2) 6.1i Architecture Wizard, DCM - "ERROR: Only Low Frequency mode is valid for Cascading in Series. Please enter an Input Clock Frequency value within the valid Low Frequency Range...". (Xilinx Answer 19301)
(SP2) 6.1i Architecture Wizard, DCM - The 2X feedback is not available for Virtex-II Pro devices. Why? (Xilinx Answer 19302)

BitGen

(SP2) 6.1i BitGen - Revise BitGen settings for Spartan-3 LVDS/RSDS standard to meet specifications. (Xilinx Answer 19204)
(SP2) 6.1i BitGen - To ensure that the PMA_SPEED attribute setting functions correctly for GT10 in Virtex-II Pro X designs, BitGen must be updated. (Xilinx Answer 19205)
(SP2) 6.1i iMPACT/BitGen - Generating qvirtex2 and qrvirtex2 bitstreams or assigning them in iMPACT results in "WARNING:Bitstream:100 - Could not determine proper JTAG IDCODE from family name". (Xilinx Answer 19202)
(SP2) 6.1i SP3 BitGen - The "-intstyle" option prevents the display of all warnings and error messages, hiding possible problems from users. (Xilinx Answer 18844)
(SP1) 6.1i SP3 - "ERROR:BitGen:145 - Pin R5 is a persistent pin, but a component exists in its IOB. Please rerun PAR with the persistent pins prohibited from use." (Xilinx Answer 18837)

CompXLib

(SP1) 6.2i CompXLib - "ERROR:cxl[env]:15- invalid MODELSIM env value detected." (Xilinx Answer 18233)

CPLD

(SP3) 6.2i CPLD CoolRunner-II - XC2C32/XC2C64 new device support for MLF package (QF32/QF48). (Xilinx Answer 18907)
(SP3) 6.2i PACE CoolRunner-II - XC2C32 PC44 pin 24 does not exist in the package view. (Xilinx Answer 19430)
(SP3) 6.2i TSim CoolRunner XPLA3 - Input register fails in timing simulation. (Xilinx Answer 19431)
(SP2) 6.2i CPLDFit - HTML reports link features are available for US English only. (Xilinx Answer 18772)
(SP2) 6.2i CPLD CoolRunner-II Project Navigator - Default for speed template has changed to disable Fast Input Registers. (Xilinx Answer 19183)
(SP1) 6.2i CPLD CoolRunner-II - XC2C32/XC2C64 new device support for MLF package (QF32/QF48). (Xilinx Answer 18907)
(SP1) 6.2i CPLDFit - "ERROR:Cpld:1106 - Signal 'SCLK' attached to BUFG drives both an active-high and active-low CLOCK." (Xilinx Answer 18993)
(SP1) 6.2i CPLD - TSim: "Vsim - instance does not have generic named 'tperiod_clk_posedge', failed to find matching specify timing constraint." (Xilinx Answer 18797)
(SP1) 6.1i CPLD BSDLAnno - CoolRunner-II BSDL files do not have signal annotation. (Xilinx Answer 18805)
(SP1) CoolRunner-II BSDL - An XC2C384 FT256 BSDL file fails JTAG operations such as EXTEST, INTEST, etc. (Xilinx Answer 18921)

Data2MEM

(SP3) 6.1i Data2MEM - Data2MEM does not complete successfully if the word "boot" is used anywhere in the path. (Xilinx Answer 18841)
(SP2) 6.1i Data2MEM - Data2MEM does not complete successfully if the word "boot" is used anywhere in the path. (Xilinx Answer 18841)

Floorplanner

(SP2) 6.2i Floorplanner - Floorplanner crashes with "FATAL ERROR GUI Utilities: Win App ...." when writing constraint to UCF. (Xilinx Answer 18994)

FPGA Editor

(SP2) 6.2i FPGA Editor - Probing error 178, "Could not route probe..." and warning 561, "Can't find compatible IO standard...". (Xilinx Answer 19141)

IBISWriter

(SP2) 6.2i SP2 IBISWriter - Spartan-3 DCI input models show unexpected results. (Xilinx Answer 19238)

iMPACT

(SP3) 6.2i iMPACT - Loading a CDF file causes a "BYTE SWAP not enabled" message. (Xilinx Answer 19163)
(SP3) 6.1i SP2 iMPACT - "ERROR: Unsupported XSVF command" occurs when I generate an XSVF file using playxsvf v4.11. (Xilinx Answer 18565)
(SP3) 6.2i iMPACT - Programming xc1800 PROM with Automatic Checksum Insertion enabled results in "ERROR:iMPACT:583". (Xilinx Answer 19435)
(SP3) 6.2i iMPACT - Platform Flash PROM XCF00P "Parallel Mode" Program Option does not work. (Xilinx Answer 19390)
(SP2) 6.1i iMPACT/PROMGen - Adding multiple MCS files in one revision spanning more than two PROMs causes iMPACT "ERROR:1836/1840". (Xilinx Answer 18923)
(SP2) 6.1i iMPACT - Cannot perform operations on any device in front of XCCACE. (Xilinx Answer 19090)
(SP2) 6.1i SP3 iMPACT - Compressed MCS file does not reduce PROM utilization display, or generation of compressed PROM file fails with "ERROR:Bitstream:25 ...". (Xilinx Answer 19206)
(SP2) 6.2i SP1 iMPACT- Initialize JTAG chain that contains third-party BSDL file results in "ERROR:IMPACT - syntax error at line xxx". (Xilinx Answer 19060)
(SP2) 6.2i iMPACT - Improved iMPACT readback verify operation for designs containing memory elements results in Done pin dropping low during FPGA verify operation. (Xilinx Answer 19207)
(SP2) 6.1i iMPACT - Programming User Code for XC1800 PROMs results in "ERROR:iMPACT:583 - '1': The idcode read from the device does not match the idcode in the bsdl File". (Xilinx Answer 19208)
(SP2) 6.2i iMPACT - SVF file generation for compressed 32MB Platform flash PROMs (XCF32P) takes a long time. (Xilinx Answer 18724)
(SP1) 6.1i iMPACT - A crash occurs when I toggle in concurrent mode for an XCFP PROM in BSCAN File Generation Mode with automatic checksum insertion enabled. (Xilinx Answer 18729)
(SP1) 6.1i SP2 iMPACT - "ERROR: Unsupported XSVF command" is reported when I generate an XSVF file using playxsvf v4.11. (Xilinx Answer 18565)
(SP1) 6.1i iMPACT - Verify fails for a design that utilizes SRL16 or LUT RAM (Distributed RAM), even though the design functions correctly. (Xilinx Answer 18725)
(SP1) 6.1i iMPACT - The JTAG USERCODE cannot be read after read protection is set for the 18V00 or Platform Flash XCF PROMs. (Xilinx Answer 18726)
(SP1) 6.1i iMPACT - An iMPACT-generated system ACE CF file does not program a Spartan-3 device. (Xilinx Answer 18925)
(SP1) 6.1i iMPACT/PROMGen - Adding multiple MCS files in one revision spanning more than two PROMs causes iMPACT "ERROR:1836/1840". (Xilinx Answer 18923)

Incremental Design

(SP2) 6.2i SP2 Incremental Design - MAP re-implements AREA_GROUPS even though 100% of slices are guided. (Xilinx Answer 18758)
(SP2) 6.2i SP2 Incremental Design - Area Groups with FMAP and/or KEEP_HIERARCHY properties might have increased levels of logic. (Xilinx Answer 19203)

MAP

(SP2) 6.2i Virtex-II Pro MAP - A fix is available to support override tie-off values for individual pins on a bus. (Xilinx Answer 19281)
(SP2) 6.1i Virtex-II MAP - "FATAL_ERROR:Pack:pksvrbaseslice.c:249:1.16 - Problem building usage for comp ...". (Xilinx Answer 18447)
(SP2) 6.2i MAP - Interaction between KEEP_HIERARCHY and Directed Routing leads to packing problem. (Xilinx Answer 19282)
(SP2) 6.2i Virtex-II Pro MAP - MAP fails in Phase 10.18 when using -timing option. (Xilinx Answer 19288)
(SP2) 6.2i Virtex-II MAP - Timing Driven Mapping (map -timing) fails when PROHIBIT constraints are used. (Xilinx Answer 19299)
(SP1) 6.1i Virtex-II MAP - "FATAL_ERROR:Pack:pksvrbaseslice.c:249:1.16 - Problem building usage for comp ...". (Xilinx Answer 18447)
(SP1) 6.1i Virtex-II MAP - "ERROR:DesignRules:368 - Netcheck: Sourceless. Net xxx has no source." (Xilinx Answer 19048)
(SP1) 6.1i Virtex-II MAP - Use of the timing-driven packing option causes design to fail and report: "Error: Unable to swap OTCLK in IOB". (Xilinx Answer 18782)
(SP1) 6.1i Virtex-II MAP - Timing driven MAP crashes while "Running timing-driven packing...". (Xilinx Answer 19049)

NetGen

(SP3) 6.2i SP2 NetGen - Error message: "Cannot correlate logic element '"U1/U1/SLAVEBUF.DIFFIN" (tag=7 in view "FRAGCOVERED")' is with this component 'in_n' cannot continue hierarchical correlation)". (Xilinx Answer 19426)

NGDBuild

(SP3) 6.1is2 NGDBuild - On Linux and Solaris, following error and segmentation fault occurs: "EXCEPTION:Xdm:xdm_stubread.c...". (Xilinx Answer 18514)

PACE

(SP3) 6.2i PACE - Unable to perform SSO analysis for Virtex-II Pro FG676 package. (Xilinx Answer 19219)
(SP2) 6.2i PACE - Invalid drive and slew rate can be entered. (Xilinx Answer 19248)
(SP2) 6.2i PACE - Duplicate LOC constraints are added to the UCF. (Xilinx Answer 19249)
(SP2) 6.2i PACE - Crashes on a design that has OBUFTDS in a schematic. (Xilinx Answer 18625)
(SP1) 6.2i PACE - HDL syntax is not honored when CSV data is read into new design. (Xilinx Answer 18984)
(SP1) 6.2i PACE - After I place a bus, the Design Object List window shows pins as placed, but individual pins are not displayed as placed. (Xilinx Answer 18985)

PAR

(SP3) 6.1i Virtex-II PAR - Router fails with error message: "FATAL_ERROR:Ncd:basncsignal.c:283:1.39.8.1 - Could not find a bel for a signal". (Xilinx Answer 19044)
(SP3) 6.2i PAR - Router automatic hold time correction fixes some errors, but creates new ones. (Xilinx Answer 19478)
(SP3) 6.2i Spartan-3 MAP - When I run MAP with -timing option, error occurs: "ERROR:Place:baspltctask.c:261:1.36.4.1 - Error : '3'". (Xilinx Answer 19213)
(SP3) 6.2i Spartan-3 PAR - Incorrect Vccint in pad report for Spartan-3. (Xilinx Answer 19479)
(SP3) 6.2i PAR - PAR fails when timing driven mapping is combined with extra effort (-xe). (Xilinx Answer 18996)
(SP3) 6.2i Spartan-3 PAR - IOB local clock not routed correctly. (Xilinx Answer 19313)
(SP3) 6.2i Virtex-II PAR - Placer check rejects 512x36 BRAM vs. MULT pair. (Xilinx Answer 19370)
(SP2) 6.1i Virtex-II, Spartan-3 PAR - Improvements have been made to local clock routing for Virtex-II and Virtex-II Pro. (Xilinx Answer 19287)
(SP2) 6.2i Virtex-II PAR - Suboptimal automatic placement of DCMs. (Xilinx Answer 19298)
(SP1) 6.1i Spartan-3 PAR - An RPM range constraint is rejected during constraint resolution. (Xilinx Answer 18682)
(SP1) 6.1i Virtex-II PAR - The placer crashes during phase 2.2. (Xilinx Answer 19050)
(SP1) 6.1i Spartan-3 PAR - Suboptimal carry chain placement in Spartan-3 devices results in reduced frequency. (Xilinx Answer 18781)
(SP1) 6.1i PAR - Clock routing does not utilize global resources during final assembly on a Modular Design. (Xilinx Answer 18073)
(SP16.1i PAR - The pad report displays an incorrect drive strength value. (Xilinx Answer 18763)
(SP1) 6.1i Spartan-3 PAR - Slice utilization numbers in the Spartan-3 PAR report are confusing. (Xilinx Answer 19004)

PrimeTime

(SP2) 6.2i PrimeTime - clock_latency is not calculated correctly for specific DCM usage (CLK90, CLK180,CLK270). (Xilinx Answer 19246)
(SP2) 6.2i PrimeTime - Correlation between PrimeTime and TRCE is off by 1 clock cycle for OFFSET IN paths with DCM fixed phase shift. (Xilinx Answer 19247)
(SP1) 6.1i PrimeTime/Create_SDC - During translation, a problem with the bus delimiters occurs. (Xilinx Answer 18980)
(SP1) 6.2i PrimeTime/Create_SDC - PrimeTime Fails to read the constraints for comments appearing without pound sign ("#"). (Xilinx Answer 18981)
(SP1) 6.2i PrimeTime - "Error: Invalid waveform. Edges must be an even number." (Xilinx Answer 18982)
(SP1) 6.2i PrimeTime/Create_SDC - An OFFSET constraint with a LOW keyword is translated incorrectly. (Xilinx Answer 18983)

Project Navigator

(SP3) 6.1i ISE - Constraint files with upper case ".UCF" extension are ignored when implementing a design in Project Navigator. (Xilinx Answer 18856)
(SP2) 6.1i ISE - The CPLD Fitter report is not available through Project Navigator if the design fails to fit. (Xilinx Answer 17973)
(SP1) 6.1i ISE - A testbench is not recognized and associated with a project source in Project Navigator. (Xilinx Answer 18348)
(SP1) 6.1i ISE - Adding an EDIF from ePD3.0 causes Project Navigator to issue a fatal error. (Xilinx Answer 18684)

PROMGen

(SP3) 6.2i PROMGen - JDRIVE, ATE, or third-party programmer reports "ISC file is invalid or DATA_CRC checksum is incorrect". (Xilinx Answer 19372)

Simulation

(SP3) 6.2i SP2 UniSim, Virtex-II Pro X/RocketIO X - Getting Xs on the PMARXLOCK during a behavioral simulation. (Xilinx Answer 19425)

Speed Files

(SP3) 6.2i Speed Files/Timing Analyzer/trce - The "P" and "N" sides of differential pairs have different timing for Spartan-3. (Xilinx Answer 19472)
(SP3) 6.2i Spartan-3 Speed Files/Timing - What is new in the 1.32 version? (Xilinx Answer 19475)
(SP2) 6.2i Speed Files/Virtex-II Pro X - MGT10 delays were under reported (Update to version 1.86). (Xilinx Answer 19250)
(SP2) 6.2i SP2 Speed Files - What speed files are currently installed for Virtex/-II and Spartan-II/-3 device families in ISE? (Xilinx Answer 12201)

StateCAD

(SP1) 6.1i SP3 StateCAD - Opening a state diagram causes: "File Corrupted: Invalid (object/action) operators read from file [vetarget], [synopsis].". (Xilinx Answer 18628)

Timing

(SP3) 6.2i Timing Analyzer/TRCE/PAR - Long run times occur, or "ERROR:Portability:3 This Xilinx application has run out of memory..." is reported (Xilinx Answer 11749)
(SP3) 6.2i Timing Analyzer/Speed files/Trce - Tdcmino not calculated correctly with the Duty Cycle Distortion macro in the feedback path. (Xilinx Answer 19476)
(SP2) 6.2i Timing Analyzer/Spartan-3 - Tdcmino values are too small for Spartan-3. (Xilinx Answer 19251)

XPower

(SP3) 6.2i XPower - Power for a single Multi-Gigibit Transceiver (MGT) is equal to multiple MGTs. (Xilinx Answer 19439)
(SP1) 6.2i XPower - The Spartan-3 default Vccaux value is incorrect. (Xilinx Answer 18750)

XST

(SP3) 6.2i XST - My EDK designs are incorrectly counting the address for caches when using the PLB IP interfaces. (Xilinx Answer 19194)
(SP3) 6.1i XST - Attributes on VHDL/schematic components incorrectly override attributes placed on instances. (Xilinx Answer 18350)
(SP3) 6.2i XST - XST is not considering LUT delays during timing for Spartan-3. (Xilinx Answer 19264)
(SP3) 6.2i XST - XST generates incorrect logic for signed comparison operations. (Xilinx Answer 19187)
(SP3) 6.2i XST Virtex-II Pro X RocketIO X - Transceiver design in VHDL does not function (TXOUTCLK is not produced). (Xilinx Answer 19332)
(SP2) 6.1i XST - Incorrect logic generated when using the conv_std_logic_vector function on a signed integer. (Xilinx Answer 18673)
(SP2) 6.1i XST - Attributes on VHDL/schematic components incorrectly override attributes placed on instances. (Xilinx Answer 18350)
(SP2) 6.2i XST - XST handles Verilog parameters incorrectly when a slice of the parameter is used and has the direction [0:n]. (Xilinx Answer 19064)
(SP2) 6.2i XST - XST swaps bits of unconstrained arrays in VHDL (LSB<=>MSB). (Xilinx Answer 19184)
(SP2) 6.2i XST - Extremely long run time for designs that contain many lines of code. (Xilinx Answer 19185)
(SP2) 6.2i XST - XST generates incorrect logic under certain arithmetic conditions. (Xilinx Answer 19186)
(SP2) 6.2i XST - XST generates incorrect logic for signed comparison operations. (Xilinx Answer 19187)
(SP1) 6.1i XST - "ERROR:NgdBuild:455 - logical net 'N17' has multiple drivers/ERROR:NgdBuild:466 - input pad net 'N17' has illegal connection." (Xilinx Answer 13206)
(SP1) 6.1i XST - XST generates incorrect logic for expressions involving signed numbers. (Xilinx Answer 18947)
(SP1) 6.2i XST - Is syn_encoding safe supported in XST? (Xilinx Answer 18966)
(SP1) 6.2i XST - "ERROR:Xst:1548 - file.vhd line xx: Negative range in type of signal <h> is not supported." (Xilinx Answer 18974)
(SP1) 6.2i XST - XST generates incorrect logic from complex synchronization expression in the process. (Xilinx Answer 18992)
(SP1) 6.2i XST - During incremental synthesis, XST is not generating a new top-level NGC file after changes to source files are made. (Xilinx Answer 18494)
AR# 19001
Date Created 02/19/2004
Last Updated 04/27/2006
Status Archive
Type General Article