UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 19020

Virtex-II Pro X RocketIO - OC-192 support for engineering samples

Description

General Description: 

How can I support OC-192 data rates with Virtex-II Pro X engineering samples (ES) since the OC-192 primitives are not available?

Solution

You can run the RocketIO X transceiver with a 5-byte interface at ~250 MHz to support OC-192 rates. Use the GT10_CUSTOM primitive and set the following: 

 

Set the PMA_SPEED attribute to 13_40.  

 

Set a 5-byte interface: 

* Drive RXDATAWIDTH, TXDATAWIDTH pins to 2'b10: this sets the fabric width to 40 bits 

* Drive RXINTDATAWIDTH, TXINTDATAWIDTH pins to 2'b11: this sets the internal bus width to 40 bits 

* Disable encoding and decoding: 

- set TXENC8B10BUSE=0, TXENC64B66BUSE=0 

- set RXDEC8B10BUSE=0, RXDEC64B66BUSE=0 

* Concatenate TX and RX signals to create the data buses: 

- TXDATA - {TXCHARDISPMODE[n], TXCHARDISPVAL[n], TXDATA[8*(n+1)-1:n*8]} where n= 3 downto 0 

- RXDATA - {RXCHARISK[n], RXRUNDISP[n], TXDATA[8*(n+1)-1:n*8]} where n= 3 to 0 

This can be done in the fabric and is the normal use model for any standard that uses 10 bit characters instead of eight.

AR# 19020
Date Created 09/03/2007
Last Updated 05/16/2014
Status Archive
Type General Article