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AR# 19027

LogiCORE MII to RMII Core v1.00a - Data misalignment can occur when used with OPB EMAC core and problems with asynchronous assertion of CRS_DV


General Description: 

When using the MII to RMII Shim core v1.00a with the OPB EMAC core in full-duplex-only mode, data can become misaligned. The misalignment occurs if there are "0" IDLE dibits between the assertion of CRS_DV and the preamble. This affects the receive side only and in all configurations, agile, fixed 10 Mb/s and fixed 100 Mb/s.  


Another issue exists in the MII to RMII Shim core v1.00a in which an asynchronous assertion of CRS_DV can lead to metastability.


Both of the above issues will be fixed in the MII to RMII core in EDK 6.2i Service Pack 1. 


Until then, you can install the following patch that fixes the above two issues for configurations using fixed throughput of 100 Mb/s. To resolve these issues, apply the patch to any version of EDK prior to EDK 6.2i SP1 following the directions for PC and UNIX below: 








Installation Instructions 


1. Navigate to existing MII to RMII VHDL source: 

For PC: %XILINX_EDK%\hw\XilinxProcessorIPLib\pcores\mii_to_rmii_v1_00_a\hdl\vhdl 

For UNIX: $XILINX_EDK\hw\XilinxProcessorIPLib\pcores\mii_to_rmii_v1_00_a\hdl\vhdl 


2. Rename the "rmii_rx_fixed.vhd" file to "rmii_rx_fixed_broken.vhd". 

3. Copy the "rmii_rx_fixed.vhd" file included in this patch to the vhdl directory. 

4. Launch EDK and open the project. 

5. From the drop-down menu, select "Tools" -> "Clean" -> "Netlist" and then select the "OK" button in the pop-up box. 

6. From the drop-down menu select "Tools" -> "Generate Bitstream". This should be sufficient to cause the tools to resynthesize the MII_to_RMII core. 

7. Resume using EDK as before.

AR# 19027
Date Created 09/03/2007
Last Updated 05/16/2014
Status Archive
Type General Article