UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 19080

6.2 EDK, UART 16550 or 16450 - C_HAS_EXTERNAL_XIN and C_HAS_EXTERNAL_RCLK are incorrect due to auto-update

Description

Keywords: MHS, UART, 16550, 16450, C_HAS_EXTERNAL_XIN, C_HAS_EXTERNAL_RCLK

Urgency: Standard

General Description:
If my MHS file contains a UART 16550 or 16450, PlatGen writes the following parameters based on whether the ports "xin" and "rclk" are included in the MHS:

C_HAS_EXTERNAL_XIN and C_HAS_EXTERNAL_RCLK

If the ports have been specified in my design, regardless of the connection, PlatGen specifies the parameter value of "1." This can cause the UART to behave incorrectly if the ports are incorrectly connected.

In the past, I have tied these unused inputs to net_gnd. Unfortunately, this now sets these parameters to "1" instead of to the "0" default. I tried setting a value for the parameter in the MHS, but this does not help, as the value is overridden.

Solution

To avoid this problem, delete the ports "rclk" and "xin" in the "system.mhs" file that your design does not use.

This problem is fixed in the latest 6.2 EDK Service Pack, available at:
http://www.xilinx.com/ise/embedded/edk.htm.
The first service pack containing the fix is EDK 6.2 Service Pack 1.
AR# 19080
Date Created 03/03/2004
Last Updated 04/09/2007
Status Archive
Type General Article