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AR# 19139

XST - XST creates incorrect logic when using signed data types in Verilog

Description

XST will improperly sign extend signed data type signals when signed and unsigned data type operands are used together in an operation:

output [5:0] O;

input [5:0] in1;

input signed [3:0] in2;

assign O = in1 + in2;

In the above example, XST will improperly sign extend in1.

Solution

In the Verilog 2001 standard, if signed and unsigned operands are used in an operation, then the operation becomes unsigned and the signed data type turns into an unsigned data type. Do not mix signed and unsigned data types when doing operations. If signed and unsigned have to be mixed, then use an intermediate signal:

:

:

wire signed [3:0] a;

wire [3:0] b;

wire [7:0] c;

wire [7:0] d;

assign c = a * b;

:

:

change to:

:

:

wire signed [3:0] a;

wire [3:0] a_temp;

wire [3:0] b;

wire [7:0] c;

wire [7:0] d;

assign a_temp = a;

assign c = a_temp * b;

:

:

AR# 19139
Date Created 09/03/2007
Last Updated 12/15/2012
Status Active
Type General Article