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AR# 19187

6.2i XST - XST generates incorrect logic for signed comparison operations

Description

Keywords: sign, VHDL, operator, wrong

Urgency: Standard

General Description:
XST generates incorrect logic for signed comparison operations, as shown in the following example:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity accup_8_loooolo is
port(
a : in std_logic_vector(18 downto 0);
b: in std_logic_vector(18 downto 0);
q : out std_logic;
clk : in std_logic
);
end accup_8_loooolo;

architecture archi of accup_8_loooolo is
signal tmp :std_logic_vector(18 downto 0);

begin
tmp <= "1111111111111111111";
q<='1' when ( signed(a) > signed(tmp) ) else '0';
end;

Solution

Unfortunately, there is no easy work around for this issue for signed data types in VHDL. One possible solution is to create your own vector sign and extend the bit to mimic the signed data type.

This problem has been fixed in the latest 6.2i Service Pack available at:
http://support.xilinx.com/xlnx/xil_sw_updates_home.jsp
The first service pack containing the fix is 6.2i Service Pack 3.
AR# 19187
Date Created 03/22/2004
Last Updated 07/18/2007
Status Archive
Type General Article