This Answer Record describes the improvements made to the PLB Gigabit Ethernet MAC (PLB GEMAC) core in EDK 6.2i Service Pack 1.
A new version of the PLB GEMAC is introduced in EDK 6.2i Service Pack 1. The new version is plb_gemac_v1_01_a. More information on EDK 6.2i SP1 is available at:
The following bug fixes and enhancements are included in the EDK 6.2i SP1 release of v1.01a of the PLB GEMAC core:
- The new Data Re-alignment Engine (DRE) was added to the IPIF. This removes the need to perform buffer copying in the VxWorks adapters (Level 2 drivers). This significantly increases performance when SG DMA and large packets are used, while at the same time decreasing CPU utilization.
- GMII and TBI interface registers and clock management circuitry were added.
- An unused Freeze input port was removed.
- Top-level parameters were changed so that RX Packet FIFO and TX Packet FIFO depths are broken out separately.
- The design was changed to prevent overflowing of the RX Length Register FIFO and allow RX Packet FIFO overflow detection. The resulting change has the following effects:
* Data corruption no longer occurs.
* Receive performance is significantly increased.
* Sporadic failures of the RX CRC Error Interrupt are eliminated.
* The RX Max Length Error Interrupt is allowed to detect received frames that exceed the maximum length when RX Jumbo Frames is disabled.
- The data sheet was updated as follows:
* A reference to the design data format was changed from "VHDL" to "NGC netlists, VHLD wrapper".
* Default settings now match the MPD file.
* Constraint, Resource, and Performance information was added.
* References to TX Pad Enable/Disable capability were removed.
* References to Receive Error Override, which was already functional, was added.
* A reference to C_MAC_FIFO_DEPTH parameter was added.
* A single IPIF FIFO depth parameter was converted into separate parameters for RX and TX.
* Freeze references were removed.