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AR# 19221

6.2is1 XST General - "ERROR:HDLParsers:164 - <coregen_core>.vhd Line 135. parse error, unexpected $"

Description

Keywords: synthesize, synthesis, COREGen, CORE Generator

Urgency: Standard

General Description:
When I am synthesizing a COREGen Core, the following error occurs in XST:

"ERROR:HDLParsers:164 - <coregen_core>.vhd Line 135. parse error, unexpected $"

Solution

1

To resolve this error, add the following compiler directives as shown to the "<CoreGen_core>.vhd" file:

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

-- add the off directive right after the ieee libraries and before the Xilinx CoreLib
-- synopsys translate_off

Library XilinxCoreLib;

-- add the on directive right before the entity declaration
-- synopsys translate_on

ENTITY dummy IS
port (
addra: IN std_logic_VECTOR(10 downto 0);
addrb: IN std_logic_VECTOR(10 downto 0);
clka: IN std_logic;
clkb: IN std_logic;
dina: IN std_logic_VECTOR(3 downto 0);
doutb: OUT std_logic_VECTOR(3 downto 0);
wea: IN std_logic);
END dummy;

ARCHITECTURE dummy_a OF dummy IS

-- add the off directive right after the architecture but before the component declarations
-- synopsys translate_off

component wrapped_dummy
port (
addra: IN std_logic_VECTOR(10 downto 0);
addrb: IN std_logic_VECTOR(10 downto 0);
clka: IN std_logic;
clkb: IN std_logic;
dina: IN std_logic_VECTOR(3 downto 0);
doutb: OUT std_logic_VECTOR(3 downto 0);
wea: IN std_logic);
end component;

-- Configuration specification
for all : wrapped_dummy use entity XilinxCoreLib.blkmemdp_v5_0(behavioral)
generic map(
c_reg_inputsb => 0,
c_reg_inputsa => 0,
c_has_ndb => 0,
c_has_nda => 0,
c_ytop_addr => "1024",
c_has_rfdb => 0,
c_has_rfda => 0,
c_yena_is_high => 1,
c_ywea_is_high => 1,
c_yclka_is_rising => 1,
c_yhierarchy => "hierarchy1",
c_ysinita_is_high => 1,
c_ybottom_addr => "0",
c_width_b => 4,
c_width_a => 4,
c_sinita_value => "0",
c_sinitb_value => "0",
c_limit_data_pitch => 18,
c_write_modeb => 0,
c_write_modea => 0,
c_has_rdyb => 0,
c_has_rdya => 0,
c_yuse_single_primitive => 1,
c_addra_width => 11,
c_addrb_width => 11,
c_has_limit_data_pitch => 0,
c_default_data => "0",
c_pipe_stages_b => 0,
c_yweb_is_high => 1,
c_yenb_is_high => 1,
c_pipe_stages_a => 0,
c_yclkb_is_rising => 1,
c_enable_rlocs => 0,
c_ysinitb_is_high => 1,
c_has_web => 0,
c_has_default_data => 1,
c_has_sinitb => 0,
c_has_wea => 1,
c_has_sinita => 0,
c_has_dinb => 0,
c_has_dina => 1,
c_ymake_bmm => 0,
c_has_enb => 0,
c_has_ena => 0,
c_depth_b => 2048,
c_mem_init_file => "mif_file_16_1",
c_depth_a => 2048,
c_has_doutb => 1,
c_has_douta => 0,
c_yprimitive_type => "1kx4");

-- add the on directive right after the component declarations and the configuration specification and right before the BEGIN
-- synopsys translate_on

BEGIN

-- add the off directive right after the BEGIN and before the component instantiations
-- synopsys translate_off

U0 : wrapped_dummy
port map (
addra => addra,
addrb => addrb,
clka => clka,
clkb => clkb,
dina => dina,
doutb => doutb,
wea => wea);

-- add the on directive right before the END
-- synopsys translate_on

END dummy_a;



This problem has been noted and will be fixed in an upcoming release.

2

The above error message will also occur if a block or region of VHDL code is not properly terminated. The most common blocks of VHDL code are entities, architectures, packages, package bodies, functions, procedures and processes. Each of these blocks has a distinct beginning and ending. Also architectures, functions, procedures and processes have "declarative" regions that end with the key word "begin." If one of these blocks does not properly end, then the following VHDL code is considered to still be in the same block of code. When the end of the file is reached, the synthesis tool is still expecting the block of code to end or is not expecting the end of the file.

Review your HDL code to ensure that all regions of code have their proper termination.
AR# 19221
Date Created 03/29/2004
Last Updated 07/18/2007
Status Archive
Type General Article