This Answer Record describes improvements made in the OPB 10/100 Ethernet MAC (opb_ethernet_v1_01_a) in EDK 6.2.02i.
Please refer to (Xilinx Answer 19231) for improvements that were made to the OPB 10/100 EMAC v1.01a core in EDK 6.2.01i.
The following bug fixes/enhancements are in the EDK 6.2i SP2 release of v1.01a of the OPB EMAC v1.01a core:
- Included a fix for a half duplex loop-back problem that was introduced as part of a fix in EDK 6.2.01i.
- The COREGen asynchronous FIFO netlist files used by this core have been updated to a more recent version. This change does not affect the user interface.
- Support was added for qvirtex2, qrvirtex2, and Virtex-4 device families.
- The MII Management interface for accessing PHY registers was changed to detect and report a no response to a register read. MII control register bit 13 is set to indicate a read error.
- A change in this release allows the use of the receive automatic PAD and CRC field stripping mode.
- A change in this release allows the selection of 16, 32 or 64 deep MAC FIFOs when using a Virtex, Virtex-E, Spartan-II, and Spartan-IIE. This was restricted to 16 deep for these devices in the previous release. All three sizes remain available for Virtex-II, Spartan-3, and Virtex-II Pro devices.
- A new generic (C_MIIM_CLKDVD) was made available to allow optimization of frequency generation for the PHY register read and write clock. The default value is "11111", which is identical to previous operation. Please refer to the data sheet for information about changing this value based on OPB clock frequency.
- Input port OPB_MnGrant was changed to the correct name OPB_MGrant. This signal is automatically connected in XPS and should not affect existing systems.