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AR# 19254

6.1.1 System Generator for DSP - "Error: A block received a data word with the valid bit set to true, but the data is in an indeterminate ("don't care") state"

Description

General Description: 

When the output of my black box is unknown ("U") or undefined ("X''), an error reports that a block received a data word with the valid bit set to true, but the data is in an indeterminate ("don't care") state. Additionally, the error states: "Such a conversion is not allowed, because Boolean control signals are not allowed to enter indeterminate states." 

 

This error occurs because the unknown "U" or undefined "X" states are translated into a NaN (Not a Number) in Simulink, and some of the blocks in System Generator cannot handle NaNs.

Solution

All signals in your design should be initialized for two reasons: 

- To ensure that they all start in a known state; 

- When the design is run in hardware, all signals are initialized to a specific value. 

 

Example 

 

signal my_signal : std_logic := '0';

 

Using System Generator blocks, you can also create a configurable subsystem in Simulink that looks like a wire at generation time, but removes the NaNs for simulation. 

 

You can use the Indeterminate Probe (!def) block in the Tools library to check for the "X" or NaN. You can then use the output of the Indeterminate Probe to drive the select line of a MUX, and then drive a MUX select with that select between the original input and a constant.

 

You can also add a cleaner to your design to clean all "U" or "X" states from the outputs of the VHDL. 

 

WARNING: This can be potentially dangerous if for some reason you need to find a "U" or "X" when debugging your code. 

 

The following illustrates original source code with an unknown "U" output that causes System Generator for DSP to generate errors: 

 

library IEEE; 

use IEEE.std_logic_1164.all; 

use IEEE.numeric_std.all; 

 

entity myreg is 

port (d: in std_logic; 

q: out std_logic; 

ce: in std_logic; 

clk: in std_logic);  

end myreg; 

 

architecture behavior of myreg is 

begin 

REG_Process : process (d,clk, ce) 

variable state : std_logic := 'U'; 

begin 

if (ce='1' and rising_edge(clk)) then 

state := d; 

end if; 

q <= state; 

end process REG_Process; 

end behavior; 

 

The following is updated code with a cleaning component that removes the "U" or "X" states. This code instantiates the original component for generation while setting up the cleaning component for simulation and replacing it with a wire for generation. 

 

library IEEE; 

use IEEE.std_logic_1164.all; 

use IEEE.numeric_std.all; 

 

entity cleaner is 

generic (Sim : bit := '0'); 

port (dirty: in std_logic; 

clean: out std_logic);  

end cleaner; 

 

architecture behavior of cleaner is 

begin 

synthModel:  

if (Sim = '0') generate 

PassThrough_Process : process (dirty) 

begin 

clean <= dirty; 

end process PassThrough_Process; 

end generate; 

 

simModel:  

if (Sim = '1') generate 

Cleaning_Process : process (dirty) 

begin 

if (dirty='U') then 

clean <= '0'; 

elsif (dirty='L') then 

clean <= '0'; 

else 

clean <= dirty; 

end if; 

end process Cleaning_Process; 

end generate; 

end behavior; 

 

 

library IEEE; 

use IEEE.std_logic_1164.all; 

use IEEE.numeric_std.all; 

 

entity my_reg_w_adapter is 

port (ce: in std_logic; 

clk: in std_logic; 

d: in std_logic; 

q: out std_logic); 

end my_reg_w_adapter; 

 

architecture structural of my_reg_w_adapter is 

component cleaner 

generic (Sim : bit := '0'); 

port (dirty: in std_logic; 

clean: out std_logic); 

end component; 

component myreg 

port (ce: in std_logic; 

clk: in std_logic; 

d: in std_logic; 

q: out std_logic); 

end component; 

signal ce_net: std_logic; 

signal clk_net: std_logic; 

signal d_net: std_logic; 

signal clean_q_net: std_logic; 

signal q_net: std_logic; 

 

begin 

ce_net <= ce; 

clk_net <= clk; 

d_net <= d; 

q <= clean_q_net; 

 

C: cleaner 

-- synopsys translate_off 

generic map (Sim => '1') 

-- synopsys translate_on 

port map (dirty => q_net, 

clean => clean_q_net); 

 

R: myreg 

port map (ce => ce_net, 

clk => clk_net, 

d => d_net, 

q => q_net); 

end structural;

AR# 19254
Date Created 09/03/2007
Last Updated 05/16/2014
Status Archive
Type General Article