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AR# 19268

6.2 EDK - The BSB CLOCK_HZ setting is incorrect for my UART driver for 200MHz/67MHz clock settings

Description

Keywords: BSB, EDK, XPS, LibGen, Clock Freq, CLOCK_HZ, PLB, OPB, UART, 16550, 16450

Urgency: Standard

General Description:
The base system builder lets the me choose frequencies for the processor and the PLB bus in a PowerPC design. If I choose 200MHz for the processor and 67MHz for the PLB frequency, the CLOCK_HZ setting for the UART driver is set to 67000000. However, the dcm_module is set up with a divisor of 1.5 (of 100MHz input clock frequency), (i.e., 2/3*100=66666667).

The error introduced by this setting might be high enough to make the UART not work when connected to some systems.

Solution

Modify the CLOCK_HZ setting for the UART in the Software Platform Settings.

This problem is fixed in the latest 6.2 EDK Service Pack, available at:
http://www.xilinx.com/ise/embedded/edk.htm.
The first service pack containing the fix is EDK 6.2 Service Pack 1.
AR# 19268
Date Created 04/06/2004
Last Updated 04/09/2007
Status Archive
Type General Article