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AR# 19277

6.2 EDK - The OPB PCI Core causes a DRC error when I set FIFO address bus widths to zero (no FIFOs)

Description

Keywords: error, Parameter, C_TRIG_PCI_READ_OCC_LEVEL, DRC, FIFO

Urgency: Standard

General Description:
I am using EDK 6.2 and v1.00c of the OPB PCI core. When I set the FIFO address bus widths generics to a value of zero (meaning no FIFOs), a PlatGen DRC error is reported. The error occurs because the occupancy level generics are still being checked even though I have specified "no FIFOs". The DRC should ignore the validation/check of the occupancy levels if there are no FIFOs.

The errors are:

"Performing System level DRCs on properties...
ERROR:MDT - C:\EDK_Gm\hw\XilinxProcessorIPLib\pcores\opb_pci_v1_00_c\data\opb_pci_v2_1_0. mpd:42 - PARAMETER C_TRIG_PCI_READ_OCC_LEVEL has value 32 which does not fall in the range (1:pow(2, C_PCI2IPIF_FIFO_ABUS_WIDTH)), specified in MPD.
ERROR:MDT - C:\EDK_Gm\hw\XilinxProcessorIPLib\pcores\opb_pci_v1_00_c\data\opb_pci_v2_1_0. mpd:44 - PARAMETER C_TRIG_PCI_DATA_XFER_OCC_LEVEL has value 16 which does not fall in the range (2:pow(2, C_IPIF2PCI_FIFO_ABUS_WIDTH)-3), specified in MPD
ERROR:MDT - C:\EDK_Gm\hw\XilinxProcessorIPLib\pcores\opb_pci_v1_00_c\data\opb_pci_v2_1_0. mpd:46 - PARAMETER C_TRIG_IPIF_READ_OCC_LEVEL has value 8 which does not fall in the range (2:pow(2, C_IPIF2PCI_FIFO_ABUS_WIDTH)-4), specified in MPD
ERROR:MDT - platgen failed with errors!"

Solution

This problem is fixed in the latest 6.2 EDK Service Pack, available at:
http://www.xilinx.com/ise/embedded/edk.htm.
The first service pack containing the fix is EDK 6.2 Service Pack 1.
AR# 19277
Date Created 04/07/2004
Last Updated 04/09/2007
Status Archive
Type General Article