UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 19321

6.2 EDK, SimGen - How do I simulate an EDK design using NC-Sim? Are there any restrictions?

Description


General Description:

How do I simulate an EDK design using NC-Sim? Are there any restrictions?

Solution


Support for NC-Sim was added in EDK 6.2 Service Pack 1, available at:

http://www.xilinx.com/ise/embedded/edk.htm
The first service pack containing the fix is EDK 6.2 Service Pack 1.



Please note the following issues regarding the use of NC-Sim in EDK:

- NC-SIM is supported on Solaris and Linux when LDV 05.10-s009 or later is used. NC-SIM is supported on Windows when LDV 05.10-s012 and EDK 6.2 Service Pack 2 is used.

- Use the following commands for simulation:



VHDL Simulation



ncelab -relax -noxilinxaccl -access +rwc <configuration>

ncsim -exit -input run.file <configuration>



Verilog Simulation



ncelab -relax -noxilinxaccl -access +rwc <testbench> -timescale 1ns/1ps glbl

ncsim -exit -input run.file <testbench>



SWIFT



For SWIFT, add:

-loadpli1 swiftpli:swift_boot during ncelab



VHDL Timing Simulation with SDF



Add command:

ncsdfc system.sdf



Add command:

-sdf_cmd_file sdf.cmd during ncelab



Example "sdf.cmd" File



COMPILED_SDF_FILE = "system.sdf.X",

SCOPE = :DUT;
AR# 19321
Date Created 09/03/2007
Last Updated 11/25/2011
Status Archive
Type General Article