We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 19328

6.2/6.1 EDK, PlatGen - "ERROR:HDLParsers:164 - ../hdl/system.vhd Line xxx. parse error, unexpected IS, expecting IDENTIFIER"


Keywords: EDK, PlatGen, ERROR:HDLParsers:164, 164, HDLParsers, Parsers, parse, unexpected, IS, IDENTIFIER, MHS, syntax, XST, HDL, Compilation

Urgency: Standard

General Description:
Upon running "Generate Netlist" in EDK, I receive the following error:

* HDL Compilation *
Compiling vhdl file H:/My_Projects/XIPPI/projects/EDK6.2.1/ProMedia/icap/hdl/system.vhd in Library work.
ERROR:HDLParsers:164 - H:/My_Projects/XIPPI/projects/EDK6.2.1/ProMedia/icap/hdl/system.vhd Line 607. parse error, unexpected IS, expecting IDENTIFIER

Subsequently, PlatGen generates the following meaningless code in "system.vhd":

component is
port (
I : in std_logic;
O : out std_logic
end component;


If one has a syntax error in the port listing of the "system.mhs" file, XST will generate this confusing error.

For example, in the following ".mhs" file snippet, you will notice the user accidentally assigned DIR to be '0' (zero) instead of 'O' (the letter 'O' for Output):

PORT startup_p = dcm0_locked, DIR = 0 (number)
rather than:
PORT startup_p = dcm0_locked, DIR = O (letter)

A software change request has been filed so that XPS/PlatGen will check the syntax of the "system.mhs" file before generating invalid VHDL.
AR# 19328
Date Created 04/14/2004
Last Updated 03/08/2006
Status Archive
Type General Article