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AR# 19330

6.2 EDK - ChipScope VIO core errors out during synthesis

Description

Keywords: VIO, ChipScope, XST, error

Urgency: Standard

General Description:

When I use a ChipScope VIO core that utilizes the "sync_out" port, XST issues a compilation error.

Solution

1

To resolve this issue, edit the "chipscope_vio_v2_1_0.tcl" file as follows:

1. The ".tcl" file is located here:

%XILINX_EDK%\hw\XilinxProcessorIPLib\pcores\chipscope_vio_v1_00_a\data

2. Make the following change at line 181:

Change the following:

if { $params(C_SYNC_OUTPUT_ENABLE) > 0 } {
puts $hdl_file "sync_out => sync_in,"
set clk_needed 1

to this:

if { $params(C_SYNC_OUTPUT_ENABLE) > 0 } {
puts $hdl_file "sync_out => sync_out,"
set clk_needed 1

2

This problem is fixed in the latest 6.2 EDK Service Pack, available at:
http://www.xilinx.com/ise/embedded/edk.htm.
The first service pack containing the fix is EDK 6.2 Service Pack 2.
AR# 19330
Date Created 04/15/2004
Last Updated 04/09/2007
Status Archive
Type General Article